Data Sheet ADAU7002
Rev. B | Page 9 of 16
APPLICATIONS INFORMATION
OVERVIEW
The ADAU7002 provides stereo decimation from a 1-bit PDM
source to a 20-bit PCM audio. The downsampling ratio is fixed
at 64×. The 20-bit downsampled PCM audio is output via
standard I
2
S or TDM formats.
The input source for the ADAU7002 can be any device that has
a PDM output, such as a digital microphone. The output pins of
these microphones can connect directly to the input pins of the
ADAU7002.
CLOCKING
The ADAU7002 requires a BCLK rate that is a minimum of 64×
the LRCLK sample rate. BCLK rates of 128×, 192×, 256×, 384×,
and 512× the LRCLK rate are also supported. The ADAU7002
automatically detects the ratio between BCLK and LRCLK and
generates a PDM clock output at 64× the LRCLK rate. The
minimum sample rate is 4 kHz, and the maximum is 96 kHz,
which correspond to a PDM clock range of 256 kHz to 6.144 MHz.
Internally, all processing is done at the PDM_CLK rate.
When BCLK is removed, the ADAU7002 powers down
automatically. When BCLK is not present, the PDM_CLK
output stops.
Table 5. PDM Timing Parameters
Parameter t
MIN
t
MAX
Unit
Data Setup Time, t
SETUP
10 ns
Data Hold Time, t
HOLD
7 ns
PDM data is latched on both edges of the clock.
Figure 12. PDM Timing Diagram
SERIAL AUDIO OUTPUT INTERFACE
The ADAU7002 supports I
2
S and TDM serial output formats.
Format selection and TDM slot placement is set with the CONFIG
pin. The SDATA pin is in tristate mode, except when the port is
driving serial data based on the CONFIG pin configuration.
Table 6. TDM Slot Selection
Device Setting CONFIG Pin Configuration
I
2
S Format Tie to IOVDD
TDM Slot 1 to Slot 2 Used/Driven, 32-Bit Slots Tie to GND
TDM Slot 3 to Slot 4 Used/Driven, 32-Bit Slots Open
TDM Slot 5 to Slot 6 Used/Driven, 32-Bit Slots Tie to IOVDD through a 47 kΩ resistor
TDM Slot 7 to Slot 8 Used/Driven, 32-Bit Slots Tie to GND through a 47 kΩ resistor
RL
t
HOLD
t
SETUP
PDM_CLK
PDM_DAT
R
L
11265-012
