Data Sheet ADAU7002
Rev. B | Page 3 of 16
SPECIFICATIONS
IOVDD = 1.8 V, T
A
= 25°C, BCLK = 3.072 MHz, output = 48 kHz, I
2
S format, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DIGITAL INPUT/OUTPUT
High Level Input Voltage (V
IH
) 0.7 × IOVDD V
Low Level Input Voltage (V
IL
) 0.3 × IOVDD V
Input Leakage, High (I
IH
) BCLK and LRCLK pins 1 µA
Input Leakage, Low (I
IL
) BCLK and LRCLK pins 1 µA
Input Capacitance 5 pF
PDM_CLK 9 mA
PERFORMANCE
Dynamic Range 20 Hz to 20 kHz, −60 dB input
With A-Weighted Filter (RMS) 110 dB
Signal-to-Noise-Ratio A-weighted, fourth-order input 110 dB
Decimation Ratio 64×
Frequency Response DC to 0.45 output f
S
−0.1 +0.01 dB
Stop Band 0.566 f
S
Stop-Band Attenuation 60 dB
Group Delay 0.02 f
S
input signal 3.31 LRCLK cycles
Gain PDM to PCM 0 dB
Start-Up Time 48 LRCLK cycles
Bit Width Internal and output 20 Bits
Degrees
CLOCKING
Output Sampling Rate f
S
LRCLK pulse rate 4 48 96 kHz
BCLK
POWER SUPPLIES
Supply Voltage Range IOVDD 1.62 3.6 V
Supply Current IOVDD = 1.8 V 0.67 mA
IOVDD = 3.3 V 1.33 mA
IOVDD = 1.8 V, 16 kHz output 0.21 mA
IOVDD = 3.3 V, 16 kHz output 0.41 mA
Shutdown Current IOVDD
SD
, no input clocks 1 µA
