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CY7C057V-15AC

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CY7C056V
CY7C057V
Document #: 38-06055 Rev. ** Page 10 of 23
Data Retention Mode
The CY7C056V and CY7C057V are designed with battery
backup in mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules ensure data
retention:
1. Chip Enable (CE
)
[3]
must be held HIGH during data retention,
within V
DD
to V
DD
– 0.2V.
2. CE
must be kept between V
DD
– 0.2V and 70% of V
DD
during the power-up and power-down transitions.
3. The RAM can begin operation >t
RC
after V
DD
reaches the
minimum operating voltage (3.15 volts).
Notes:
20. t
BDD
is a calculated parameter and is the greater of t
WDD
–t
PWE
(actual) or t
DDD
–t
SD
(actual).
21. CE
= V
DD
, V
in
= V
SS
to V
DD
, T
A
= 25°C. This parameter is guaranteed but not tested.
Busy Timing
[19]
t
BHC
BUSY HIGH from CE HIGH 12 15 20 ns
t
PS
Port Set-Up for Priority 5 5 5 ns
t
WB
R/W LOW after BUSY (Slave) 0 0 0 ns
t
WH
R/W HIGH after BUSY HIGH (Slave) 11 13 15 ns
t
BDD
[20]
BUSY HIGH to Data Valid 12 15 20 ns
Interrupt Timing
[19]
t
INS
INT Set Time 12 15 20 ns
t
INR
INT Reset Time 12 15 20 ns
Semaphore Timing
t
SOP
SEM Flag Update Pulse (OE or SEM)10 10 10 ns
t
SWRD
SEM Flag Write to Read Time 5 5 5 ns
t
SPS
SEM Flag Contention Window 5 5 5 ns
t
SAA
SEM Address Access Time 12 15 20 ns
Switching Characteristics Over the Operating Range
[13]
(continued)
Parameter Description
CY7C056V
CY7C057V
Unit
-12
-15 -20
Min. Max.
Min. Max. Min. Max.
Timing
Parameter Test Conditions
[21]
Max. Unit
ICC
DR1
@ VDD
DR
= 2V 50 µA
Data Retention Mode
3.15V
3.15V
V
CC
> 2.0V
V
CC
to V
CC
– 0.2V
V
CC
CE
t
RC
V
IH
CY7C056V
CY7C057V
Document #: 38-06055 Rev. ** Page 11 of 23
Switching Waveforms
Notes:
22. R/W
is HIGH for read cycles.
23. Device is continuously selected. CE
0
= V
IL
, CE
1
=V
IH
, and B
0
, B
1
, B
2
, B
3
, WA, BA are valid. This waveform cannot be used for semaphore reads.
24. OE
= V
IL
.
25. Address valid prior to or coinciding with CE
0
transition LOW and CE
1
transition HIGH.
26. To access RAM, CE
0
= V
IL
, CE
1
=V
IH
, B
0
, B
1
, B
2
, B
3
, WA, BA are valid, and SEM = V
IH
. To access semaphore, CE
0
= V
IH
, CE
1
=V
IL
and SEM = V
IL
or CE
0
and SEM=V
IL
,
and CE
1
= B
0
= B
1
= B
2
= B
3
, =V
IH
.
t
RC
t
AA
t
OHA
DATA VALIDPREVIOUS DATA VALID
DATA OUT
ADDRESS
t
OHA
Read Cycle No. 1 (Either Port Address Access)
[22, 23, 24]
t
ACE
t
LZOE
t
DOE
t
HZOE
t
HZCE
DATA VALID
t
LZCE
t
PU
t
PD
I
SB
I
CC
DATA OUT
B
2
, B
3
, WA, BA
CE
0
, CE
1
, B
0
, B
1
,
CURRENT
Read Cycle No. 2 (Either Port CE/OE Access)
[22, 25, 26]
SELECT VALID
OE
DATA OUT
t
RC
ADDRESS
t
AA
t
OHA
CE
0
, CE
1
t
LZCE
t
ABE
t
HZCE
t
HZCE
t
ACE
t
LZCE
Read Cycle No. 3 (Either Port)
[22, 24, 25, 26]
B
0
, B
1
, B
2
,
B
3
, WA, BA
BYTE SELECT VALID
CHIP SELECT VALID
CY7C056V
CY7C057V
Document #: 38-06055 Rev. ** Page 12 of 23
Notes:
27. R/W
must be HIGH during all address transitions.
28. A write occurs during the overlap (t
SCE
or t
PWE
) of CE
0
=V
IL
and CE
1
=V
IH
or SEM=V
IL
and B
0–3
LOW.
29. t
HA
is measured from the earlier of CE
0
/CE
1
or R/W or (SEM or R/W) going HIGH at the end of Write Cycle.
30. If OE
is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
PWE
or (t
HZWE
+ t
SD
) to allow the I/O drivers to turn off and data to be placed on
the bus for the required t
SD
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
PWE
.
31. To access RAM, CE
0
= V
IL
, CE
1
=SEM = V
IH
.
32. To access byte B
0
, CE
0
= V
IL
, B
0
= V
IL
, CE
1
=SEM = V
IH
.
To access byte B
1
, CE
0
= V
IL
, B
1
= V
IL
, CE
1
=SEM = V
IH
.
To access byte B
2
, CE
0
= V
IL
, B
2
= V
IL
, CE
1
=SEM = V
IH
.
To access byte B
3
, CE
0
= V
IL
, B
3
= V
IL
, CE
1
=SEM = V
IH
.
33. Transition is measured ±150 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
34. During this period, the I/O pins are in the output state, and input signals must not be applied.
35. If the CE
0
LOW and CE
1
HIGH or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
Switching Waveforms (continued)
t
AW
t
WC
t
PWE
t
HD
t
SD
t
HA
CE
0
, CE
1
R/W
OE
DATAOUT
DATA IN
ADDRESS
t
HZOE
t
SA
t
HZWE
t
LZWE
Write Cycle No. 1: R/W Controlled Timing
[27, 28, 29, 30]
[33]
[33]
[30]
[31, 32]
NOTE 34
NOTE 34
CHIP SELECT VALID
t
AW
t
WC
t
SCE
t
HD
t
SD
t
HA
R/W
DATA IN
ADDRESS
t
SA
Write Cycle No. 2: CE Controlled Timing
[27, 28, 29, 35]
CE
0
, CE
1
[31, 32]
CHIP SELECT VALID
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CY7C057V-15AC

Mfr. #:
Buy CY7C057V-15AC
Manufacturer:
Cypress Semiconductor
Description:
IC SRAM 1.152M PARALLEL 144TQFP
Lifecycle:
New from this manufacturer.
Delivery:
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