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CY7C057V-15AC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
CY7C056V
CY7C057V
Document #: 38-06055 Rev. ** Page 13 of 23
Notes:
36. CE
0
= HIGH and CE
1
= LOW for the duration of the above timing (both write and read cycle).
37. I/O
0R
= I/O
0L
= LOW (request semaphore); CE
0R
= CE
0L
= HIGH and CE
1R
= CE
1L
=LOW.
38. Semaphores are reset (available to both ports) at cycle start.
39. If t
SPS
is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
Switching Waveforms (continued)
t
SOP
t
SAA
VALID ADRESS VALID ADRESS
t
HD
DATA
IN
VALID
DATA
OUT
VALID
t
OHA
t
AW
t
HA
t
ACE
t
SOP
t
SCE
t
SD
t
SA
t
PWE
t
SWRD
t
DOE
WRITE CYCLE READ CYCLE
OE
R/W
I/O
0
SEM
A
0
–A
2
Semaphore Read After Write Timing, Either Side
[36]
MATCH
t
SPS
A
0L
–A
2L
MATCH
R/W
L
SEM
L
A
0R
–A
2R
R/W
R
SEM
R
Timing Diagram of Semaphore Contention
[37, 38, 39]
CY7C056V
CY7C057V
Document #: 38-06055 Rev. ** Page 14 of 23
Note:
40. CE
0L
= CE
0R
= LOW; CE
1L
= CE
1R
= HIGH.
Switching Waveforms (continued)
VALID
t
DDD
t
WDD
MATCH
MATCH
R/W
R
DATA IN
R
DATA
OUTL
t
WC
ADDRESS
R
t
PWE
VALID
t
SD
t
HD
ADDRESS
L
t
PS
t
BLA
t
BHA
t
BDD
BUSY
L
Timing Diagram of Write with BUSY (M/S=HIGH)
[40]
t
PWE
R/W
BUSY
t
WB
t
WH
Write Timing with Busy Input (M/S=LOW)
CY7C056V
CY7C057V
Document #: 38-06055 Rev. ** Page 15 of 23
Note:
41. If t
PS
is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
Switching Waveforms (continued)
ADDRESS MATCH
t
PS
t
BLC
t
BHC
ADDRESS MATCH
t
PS
t
BLC
t
BHC
CE
R
ValidFirst:
ADDRESS
L, R
BUSY
R
CE
0L
, CE
1L
CE
0R
, CE
1R
BUSY
L
ADDRESS
L, R
Busy Timing Diagram No. 1 (CE Arbitration)
[41]
CE
L
Valid First:
CHIP SELECT VALID
CHIP SELECT VALID
CE
0L
, CE
1L
CE
0R
, CE
1R
CHIP SELECT VALID
CHIP SELECT VALID
ADDRESS MATCH
t
PS
ADDRESS
L
BUSY
R
ADDRESS MISMATCH
t
RC
or t
WC
t
BLA
t
BHA
ADDRESS
R
ADDRESS MATCH ADDRESS MISMATCH
t
PS
ADDRESS
L
BUSY
L
t
RC
or t
WC
t
BLA
t
BHA
ADDRESS
R
Right AddressValid First:
Busy Timing Diagram No. 2 (Address Arbitration)
[41]
Left Address Valid First:
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

CY7C057V-15AC

Mfr. #:
Buy CY7C057V-15AC
Manufacturer:
Cypress Semiconductor
Description:
IC SRAM 1.152M PARALLEL 144TQFP
Lifecycle:
New from this manufacturer.
Delivery:
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