10
LTC4212
4212f
Figure 1. ON Pin Sets the Undervoltage
Lockout Voltage Externally
3.3V
R1
10k
R2
10k
ON PIN
(a) V
CC
= 3.3V
5V
R1
20k
R2
10k
ON PIN
(b) V
CC
= 5V
12V
R1
61.9k
R2
10k
ON PIN
(c) V
CC
= 12V
4212 F01
Hot Circuit Insertion
When circuit boards are inserted into or removed from live
backplanes, the supply bypass capacitors can draw huge
transient currents from the backplane power bus as they
charge. The transient current can cause permanent dam-
age to the connector pins as well as cause glitches on the
system supply, causing other boards in the system to
reset.
The LTC4212 is designed to turn a printed circuit board’s
supply voltages ON and OFF in a controlled manner, allow-
ing the circuit board to be safely inserted or removed from
a live backplane.
Output Voltage Monitor
Unlike other LTC Hot Swap controller products, the
LTC4212 does not have an FB pin and monitors onboard
DC/DC converters via an external power supply monitor IC
such as the LTC1326-2.5 or the LTC1727. This allows
several DC/DC converters to be monitored at the same
time. The LTC4212’s PGI or power good input pin is used
to monitor the RST or comparator outputs of the monitor
IC and it can also be tied directly to the PGOOD pin of a
DC/DC converter.
Undervoltage Lockout
The LTC4212’s internal power-on reset circuit initializes
the start-up procedure and ensures the IC is in the proper
state if the input supply voltage exceeds 2.34V. If the
supply voltage falls below 2.23V, the LTC4212 is in
undervoltage lockout (UVLO) mode, and the GATE pin is
pulled low. Since the UVLO circuitry uses hysteresis, the
LTC4212 restarts after the supply voltage rises above
2.34V and the ON pin goes high.
In addition, users can utilize the ON comparator (COMP1)
or the FAULT comparator (COMP6) to effectively set up a
higher undervoltage lockout level. Figure 1 shows the
external resistive divider for the ON pin to adjust the
system’s undervoltage lockout voltage. The system will
enter the plug-in cycle after the ON pin rises above 1.316V.
The resistive divider sets the circuit to turn on when V
CC
reaches around 79% of its final value. If a different turn on
V
CC
voltage is desired change the resistive divider ratio
accordingly. The FAULT comparator can also be used to
set a higher undervoltage lockout voltage. If the FAULT
comparator is used for this purpose, the system will wait
for the input voltage to increase above the level set by the
user before starting the second timing cycle. Also, if the
input voltage drops below the set level in normal operating
mode, the electronic circuit breaker (ECB) trips and the
user must cycle the ON pin or V
CC
to restart the system.
OPERATIO
U
System Timing
System timing for the LTC4212 is generated by the TIMER
circuitry (see the Block Diagram). If the LTC4212’s inter-
nal timing circuit is off, an internal N-channel FET connects
the TIMER pin to GND. If the timing circuit is enabled, an
internal 2µA current source is then connected to the
TIMER pin to charge C
TIMER
at a rate given by Equation 1:
C Charge -Up Rate
TIMER
=
µ2A
C
TIMER
(1)
When the TIMER pin voltage reaches COMP4’s threshold
of 1.236V, the TIMER pin is reset to GND. Equation 2 gives
an expression for the timer period:
tV
C
A
TIMER
TIMER
=
µ
1 236
2
.•
(2)
As a design aid, the LTC4212’s timer period as a function
of the C
TIMER
using standard values from 3.3nF to 0.33µF
is shown in Table 1.
The C
TIMER
value is vital to ensure a proper start-up and
reliable operation. This timing period should not be exces-
sive as an output short can occur at start-up causing the
external MOSFET to overheat. A good starting point is to
11
LTC4212
4212f
set C
TIMER
= 10nF and adjust its value accordingly to suit
the specific applications.
Table 1. t
TIMER
vs C
TIMER
C
TIMER
t
TIMER
0.0033µF 2.0ms
0.0047µF 2.9ms
0.0068µF 4.2ms
0.0082µF 5.1ms
0.01µF 6.2ms
0.015µF 9.3ms
0.022µF 13.6ms
0.033µF 20.4ms
0.047µF 29.0ms
0.068µF 42.0ms
0.082µF 50.7ms
0.1µF 61.8ms
0.15µF 92.7ms
0.22µF 136ms
0.33µF 204ms
Power-Up Timeout Circuit
The power-up timeout circuit has two functions. During
power-up, it trips the circuit breaker if the DC/DC convert-
ers on the board do not power-up and do not enter
regulation on time. After normal power-up, it is configured
to trip the circuit breaker if any of the converters exit
regulation for longer than a programmable delay. Once the
circuit breaker is tripped, the LTC4212 is latched off and
the board is disconnected from the system supply. The ON
pin must be taken low for 120µs to reset the circuit breaker
and then high to reconnect the board to the backplane
supply.
The power-up timeout circuit uses three pins: PGI or
power good input pin, PGT or power good timer pin and
PGF or power good filter pin. It is enabled at the end of the
second system timing cycle, provided that the FAULT pin
is high. Prior to being enabled or if FAULT is low, the PGT
and PGF pins are pulled to GND by internal N-channel
FETs, M5 and M12 respectively. When enabled, the
power-up timeout circuit starts the power good timer,
which generates a time-out period before the PGI pin is
sampled.
OPERATIO
U
Power Good Timer
The timer consists of COMP9, M8-M12, two 5µA current
sources and 0.65V and 0.95V threshold voltages for
COMP9.
The PGI pin is normally connected to the RST output pin
or comparator outputs of an external supply monitor IC or
to the PGOOD pin of a DC/DC converter and drives a
comparator, COMP8 which has a threshold voltage of
1.236V and 28mV of hysterisis. The RST and PGOOD pins
are typically open drain pins and require an external pull-
up resistor. The upper end of the resistor must be con-
nected to a voltage greater than the upper threshold of the
PGI comparator (1.236V).
A capacitor, C
PGT
, connected from the PGT pin to ground
programs the time-out period generated by the power
good timer according to Equation 3. Table 2 shows the
power good time-out periods for a list of standard capaci-
tor values.
t
TIMEOUT
= 1.81 • C
PGT
(3)
Two 5µA current sources are switched in and out to charge
and discharge C
PGT
between 0.65V and 0.95V for 14
cycles.
Table 2. t
TIMEOUT
vs C
PGT
C
PGT
t
TIMEOUT
3.3nF 5.97ms
4.7nF 8.51ms
6.8nF 12.3ms
8.2nF 14.8ms
0.01µF 18.1ms
0.022µF 39.8ms
0.033µF 59.7ms
0.047µF 85.1ms
0.068µF 123ms
0.082µF 148ms
0.1µF 181ms
0.22µF 136ms
0.33µF 398ms
0.47µF 851ms
0.68µF 1230ms
0.82µF 1480ms
1µF 1810ms
12
LTC4212
4212f
Since the PGT is pulled to GND by M12 before the power
good circuit is enabled, the first positive ramp at the PGT
pin starts from 0V instead of the 0.65V for the subsequent
13 cycles.
Power Good Time-Out
At the end of the time-out period, the PGI pin is sampled.
M12 is turned on to discharge C
PGT
to ground. If the PGI
pin is low when sampled, the DC/DC converters have not
entered into regulation on time and the power good circuit
trips the circuit breaker to latch off the board. If PGI is high
when sampled, the converters powered up into regulation
on time and the board is left powered up. The power good
glitch filter is enabled and it monitors the PGI pin for a low,
an indication that at least one DC/DC converter has dropped
out of regulation. The glitch filter rejects low pulses
shorter than a programmable period.
Power Good Glitch Filter
A glitch filter consisting of COMP5, M5 and a 5µA current
source rejects PGI low pulses that are shorter than the
duration programmed by an external capacitor, C
PGF
,
connected from the PGF pin to GND.
Once the glitch filter is enabled, M5 is switched off
whenever PGI goes low. This allows an internal 5µA
current source to charge the capacitor at the PGF pin. If
PGI stays low for long enough, the voltage at the PGF pin
rises above the upper threshold of COMP5 (1.236V) and
causes the power good circuit to trip the circuit breaker.
For a given C
PGF
capacitance connected between PGF and
GND, the minimum low PGI pulse width needed to trip the
circuit breaker is given by:
t
PGF
= 1.236V • (C
PGF
)/5µA + 5µs (4)
An internal 5pF capacitor and stray MSOP-10 package
capacitance sets t
PGF
to 5µs nominal when C
PGF
is omit-
ted. Table 3 shows t
PGF
values for various standard
capacitors. Tying the PGF pin to ground prevents the
power good glitch filter from tripping the circuit breaker
after normal power-up.
OPERATIO
U
Table 3. t
PGF
vs C
PGF
C
PGF
t
PGF
—5µs
10pF 7.5µs
22pF 10.4µs
33pF 13.2µs
47pF 16.6µs
68pF 21.8µs
82pF 25.2µs
100pF 29.7µs
220pF 59.3µs
330pF 86.6µs
470pF 121.2µs
680pF 173µs
820pF 208µs
1nF 252µs
Soft-Start or Inrush Current Control
The LTC4212 monitors the load current by sensing the
voltage (V
CC
– V
SENSE
) developed across an external
sense resistor (R
SENSE
) connected between the V
CC
and
SENSE pins. During the second timing cycle (see Normal
Operating Sequence) a soft-start circuit turns on the
external N-channel FET gradually to keep inrush currents
in check. The soft-start circuit monitors and servos the
voltage across R
SENSE
to 50mV by either connecting a
10µA pull-up current source to the GATE pin when the
voltage across R
SENSE
is less than 50mV or discharging it
with a 10µA pull-down current source when the voltage
rises above 50mV. Therefore, the inrush current from the
backplane supply is limited to:
I
LIMIT(SOFTSTART)
= 50mV/R
SENSE
(5)
For example, I
LIMIT(SOFTSTART)
= 5A when R
SENSE
= 0.01.
Assuming that the voltage across the sense resistor does
not exceed 50mV, the voltage at the GATE pin rises at rate
given by:
V
GATE
Slew Rate = dV
GATE
/dt =10µA/C
GATE
(6)
where, C
GATE
= Power MOSFET gate input capacitance
(C
ISS
).
For example, an Si4410DY (a 30V N-channel power
MOSFET) exhibits an approximate C
GATE
of 3300pF at

LTC4212IMS#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Hot Swap Voltage Controllers Hot Swap Controller w/Power Up Timer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union