19
LTC4212
4212f
OPERATIO
U
Figure 5. LTC4212 Autoretry Application
+
V
CC
SENSE
LTC4212
9
1
10
23
87
10µF
+
10µF
2
31
5V
2.5V
1.5A
3.3V
1.5A
4212 F05
6
GATE
PGT
4
PGFTIMER
C
TIMER
0.01µF
PGI
ON
V
CC
5V
GND
Z1 = SMAJ10A (TVS)
R
AUTO
1M
R
X
10
R
SENSE
0.007
EDGE
CONNECTOR
(MALE)
M1
Si4410DY
Z1
R4
10k
R6
2.1k
R5
10k
R
G
100
FAULT
GND
+
10µF
LT1963-2.5
C
PGT
180nF
C
PGF
18pF
C
X
10nF
BACKPLANE
CONNECTOR
(FEMALE)
5
+
10µF
2
31
+
10µF
LT1963-3.3
4
3
LTC1326-2.5
GND
V
CCA
1
V
CC3
6
RST
2
V
CC25
C
AUTO
2µF
Figure 6. Autoretry Sequence
V
CC
ON
V
REF
2.34V
TIMER
GATE
DC/DC
CONVERTER
OUTPUT
V
CC
– V
SENSE
FAULT
PGT
PGI
PGF
4212 F06
12
3
456 78 109 11 12 131415 16 17 18 19
POWER GOOD
TIMER ENABLED
(C
PGT
)
POWER GOOD
TIMER ENABLED
(C
PGT
)
0.95V
0.65V
0.95V
0.65V
2ND
TIMING
CYCLE (C
TIMER
)
1ST
TIMING
CYCLE (C
TIMER
)
1.316V 1.31V
0.455V 0.455V
2ND
TIMING
CYCLE (C
TIMER
)
1ST
TIMING
CYCLE (C
TIMER
)
SOFT-START ACTIVE SOFT-START ACTIVE
V
REF
V
REF
V
REF
V
CC
– V
SENSE
=
50mV
V
CC
– V
SENSE
=
50mV
> 50mV, > 18µs
> 50mV, > 18µs
20
LTC4212
4212f
OPERATIO
U
by the SLOW COMP’s threshold, V
CB(SLOW)
= 50mV, and
occurs should a load current fault condition exist for more
than 18µs. The current level at which the electronic circuit
breaker trips is given by Equation 8:
I
V
R
mV
R
TRIP SLOW
CB SLOW
SENSE SENSE
()
()
==
50
(8)
The second trip point is set by the FAST COMP’s threshold,
V
CB(FAST)
= 150mV, and occurs during fast load current
transients that exist for 500ns or longer. The current level
at which the circuit breaker trips in this case is given by
Equation 9:
I
V
R
mV
R
TRIP FAST
CB FAST
SENSE SENSE
()
()
==
150
(9)
As a design aid, the currents at which electronic circuit
breaker trips for common values for R
SENSE
are shown in
Table 4.
Table 4. I
TRIP(SLOW)
and I
TRIP(FAST)
vs R
SENSE
R
SENSE
I
TRIP(SLOW)
I
TRIP(FAST)
0.005 10A 30A
0.006 8.3A 25A
0.007 7.1A 21A
0.008 6.3A 19A
0.009 5.6A 17A
0.01 5A 15A
For proper circuit breaker operation, Kelvin-sense PCB
connections between the sense resistor and the LTC4212’s
V
CC
and SENSE pins are strongly recommended. The
drawing in Figure 7 illustrates the correct way of making
connections between the LTC4212 and the sense resistor.
PCB layout should be balanced and symmetrical to mini-
mize wiring errors. In addition, the PCB layout for the
sense resistor should include good thermal management
techniques for optimal sense resistor power dissipation.
The power rating of the sense resistor should accommo-
date steady-state fault current levels so that the compo-
nent is not damaged before the circuit breaker trips.
Table␣ 5 in the Appendix lists sense resistors that can be
used with the LTC4212’s circuit breaker.
Calculating Circuit Breaker Trip Current
For a selected R
SENSE
value, the nominal load current that
trips the circuit breaker is given by Equation 10:
IRC-TT SENSE RESISTOR
LR251201R010F
OR EQUIVALENT
0.01, 1%, 1W
CURRENT FLOW
TO LOAD
CURRENT FLOW
TO LOAD
TO
V
CC
TO
SENSE
TRACK WIDTH W:
0.03" PER AMP
ON 1 OZ COPPER
W
4212 F07
Figure 7. Making PCB Connections to the Sense Resistor
I
V
R
mV
R
TRIP NOM
CB NOM
SENSE NOM SENSE NOM
()
()
() ()
==
50
(10)
The minimum load current that trips the circuit breaker is
given by Equation 11.
I
V
R
mV
R
TRIP MIN
CB MIN
SENSE MAX SENSE MAX
()
()
() ()
==
40
(11)
where
RR
R
SENSE MAX SENSE NOM
TOL
() ()
=+
1
100
The maximum load current that trips the circuit breaker is
given in Equation 12.
I
V
R
mV
R
TRIP MAX
CB MAX
SENSE MIN SENSE MIN
()
()
() ()
==
60
(12)
where
RR
R
SENSE MIN SENSE NOM
TOL
() ( )
•–=
1
100
21
LTC4212
4212f
OPERATIO
U
For example:
If a sense resistor with 7m ±5% R
TOL
is used for current
limiting, the nominal trip current I
TRIP(NOM)
= 7.1A. From
Equations 11 and 12, I
TRIP(MIN)
= 5.4A and I
TRIP(MAX)
=
9.02A respectively.
For proper operation and to avoid the circuit breaker
tripping unnecessarily, the minimum trip current
(I
TRIP(MIN)
) must exceed the circuit’s maximum operating
load current. For reliability purposes, the operation at the
maximum trip current (I
TRIP(MAX)
) must be evaluated
carefully. If necessary, two resistors with the same R
TOL
can be connected in parallel to yield an R
SENSE(NOM)
value
that fits the circuit requirements.
Power MOSFET Selection Criteria
To start the power MOSFET selection process, choose the
maximum drain-to-source voltage, V
DS(MAX)
, and the
maximum drain current, I
D(MAX)
of the MOSFET. The
V
DS(MAX)
rating must exceed the maximum input supply
voltage (including surges, spikes, ringing, etc.) and the
I
D(MAX)
rating must exceed the maximum short-circuit
current in the system during a fault condition. In addition,
consider three other key parameters: 1) the required gate-
source (V
GS
) voltage drive, 2) the voltage drop across the
drain-to-source on resistance, R
DS(ON)
and 3) the maxi-
mum junction temperature rating of the MOSFET.
Power MOSFETs are classified into two categories: stan-
dard MOSFETs (R
DS(ON)
specified at V
GS
= 10V) and
logic-level MOSFETs (R
DS(ON)
specified at V
GS
= 5V). The
absolute maximum rating for V
GS
is typically ±20V for
standard MOSFETs. However, the V
GS
maximum rating
for logic-level MOSFETs ranges from ±8V to ±20V de-
pending upon the manufacturer and the specific part
number. The LTC4212’s GATE overdrive as a function of
V
CC
is illustrated in the Typical Performance curves. Logic-
level MOSFETs are recommended for low supply voltage
applications and standard MOSFETs can be used for appli-
cations where supply voltage is greater than 4.75V.
Note that in some applications, the gate of the external
MOSFET can discharge faster than the output voltage
when the circuit breaker is tripped. This causes a negative
V
GS
voltage on the external MOSFET. Usually, the selected
external MOSFET should have a ±V
GS(MAX)
rating that is
higher than the operating input supply voltage to ensure
that the external MOSFET is not destroyed by a negative
V
GS
voltage. In addition, the ±V
GS(MAX)
rating of the
MOSFET must be higher than the gate overdrive voltage.
Lower ±V
GS(MAX)
rating MOSFETs can be used with the
LTC4212 if the GATE overdrive is clamped to a lower
voltage. The circuit in Figure 8 illustrates the use of zener
diodes to clamp the LTC4212’s GATE overdrive signal if
lower voltage MOSFETs are used.
V
CC
V
OUT
*USER SELECTED VOLTAGE CLAMP
(A LOW BIAS CURRENT ZENER DIODE IS RECOMMENDED)
1N4688 (5V)
1N4692 (7V): LOGIC-LEVEL MOSFET
1N4695 (9V)
1N4702 (15V): STANDARD-LEVEL MOSFET
4212 F08
R
SENSE
GATE
D2*
D1*
Q1
R
G
200
Figure 8. Optional Gate Clamp for Lower V
GS(MAX)
MOSFETs
The R
DS(ON)
of the external pass transistor should be low
to make its drain-source voltage (V
DS
) a small percentage
of V
CC
. At a V
CC
= 2.5V, V
DS
+ V
RSENSE
= 0.1V yields 4%
error at the output voltage. This restricts the choice of
MOSFETs to very low R
DS(ON)
. At higher V
CC
voltages, the
V
DS
requirement can be relaxed in which case MOSFET
package dissipation (P
D
and T
J
) may limit the value of
R
DS(ON)
. Table 6 lists some power MOSFETs that can be
used with the LTC4212.
For reliable circuit operation, the maximum junction tem-
perature (T
J(MAX)
) for a power MOSFET should not exceed
the manufacturer’s recommended value. This includes
normal mode operation, start-up, current-limit and
autoretry mode in a fault condition. Under normal condi-
tions the junction temperature of a power MOSFET is given
by Equation 13:
MOSFET Junction Temperature,
T
J(MAX)
T
A(MAX)
+ θ
JA
• P
D
(13)

LTC4212IMS#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Hot Swap Voltage Controllers Hot Swap Controller w/Power Up Timer
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