Data Sheet ADM1191
Rev. C | Page 9 of 16
VOLTAGE AND CURRENT READBACK
The ADM1191 contains the components to allow voltage and
current readback over an I
2
C bus. The voltage output of the
current sense amplifier and the voltage on the VCC pin are fed
into a 12-bit ADC via a multiplexer. The device can be instructed
to convert voltage and/or current at any time during operation
by issuing an I
2
C command or driving the CONV pin high. When
all conversions are complete, the voltage and/or current values
can be read back with 12-bit accuracy in two or three bytes.
SERIAL BUS INTERFACE
Control of the ADM1191 is carried out via the serial system
management bus (I
2
C). This interface is compatible with the I
2
C
fast mode (400 kHz maximum). The ADM1191 is connected to
this bus as a slave device, under the control of a master device.
IDENTIFYING THE ADM1191 ON THE I
2
C BUS
The ADM1191 has a 7-bit serial bus slave address. When the
device powers up, it does so with a default serial bus address.
The three MSBs of the address are set to 011; the four LSBs are
determined by the state of the A0 pin and the A1 pin. There are
16 configurations available on the A0 pin and A1 pin that corre-
spond to 16 I
2
C addresses for the four LSBs (see Table 5). This
scheme allows 16 ADM1191 devices to operate on a single I
2
C bus.
GENERAL I
2
C TIMING
Figure 16 and Figure 17 show timing diagrams for general write
and read operations using the I
2
C. The I
2
C specification defines
conditions for different types of read and write operations, which
are discussed in the Write and Read Operations section. The
general I
2
C protocol operates as follows:
1. The master initiates a data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line, SDA, while the serial clock line, SCL, remains high.
This indicates that a data stream is to follow. All slave periph-
erals connected to the serial bus respond to the start condition
and shift in the next eight bits, consisting of a 7-bit slave
address (MSB first) plus an R/
W
bit that determines the
direction of the data transfer, that is, whether data is written
to or read from the slave device (0 = write, 1 = read).
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the
low period before the ninth clock pulse, known as the
acknowledge bit, and holding it low during the high period
of this clock pulse. All other devices on the bus remain idle
while the selected device waits for data to be read from it
or written to it. If the R/
W
bit is 0, the master writes to the
slave device. If the R/
W
bit is 1, the master reads from the
slave device.
2. Data is sent over the serial bus in sequences of nine clock
pulses: eight bits of data followed by an acknowledge bit
from the slave device. Data transitions on the data line
must occur during the low period of the clock signal and
remain stable during the high period because a low-to-
high transition when the clock is high can be interpreted as
a stop signal.
If the operation is a write operation, the first data byte after
the slave address is a command byte. This tells the slave
device what to expect next. It can be an instruction, such as
telling the slave device to expect a block write, or it can be
a register address that tells the slave where subsequent data
is to be written.
Because data can flow in only one direction, as defined by
the R/
W
bit, it is not possible to send a command to a slave
device during a read operation. Before performing a read
operation, it may be necessary to first execute a write
operation to tell the slave what sort of read operation to
expect and/or the address from which data is to be read.
3. When all data bytes are read or written, stop conditions are
established. In write mode, the master pulls the data line
high during the 10
th
clock pulse to assert a stop condition.
In read mode, the master device releases the SDA line
during the SCL low period before the ninth clock pulse,
but the slave device does not pull it low. This is known as a no
acknowledge. The master then takes the data line low during
the SCL low period before the 10
th
clock pulse and then high
during the 10
th
clock pulse to assert a stop condition.
Table 5. Setting I
2
C Addresses via the A0 Pin and the A1 Pin
Base Address A1 Pin State A0 Pin State A1 Pin Logic State A0 Pin Logic State Address in Binary
1
Address in Hex
011 Ground Ground 00 00 0110000X 0x60
Ground Resistor to ground 00 01 0110001X 0x62
Ground Floating 00 10 0110010X 0x64
Ground High 00 11 0110011X 0x66
Resistor to ground Ground 01 00 0110100X 0x68
Resistor to ground Resistor to ground 01 01 0110101X 0x6A
Floating Ground 10 00 0111000X 0x70
Floating Resistor to ground 10 01 0111001X 0x72
