ADM1191-2ARMZ-R7 Datasheet ADM1191-2ARMZ-R7 | P13-P15

ADM1191 Data Sheet

Rev. C | Page 12 of 16

WRITE EXTENDED COMMAND BYTE

In the write extended command byte operation, the master

device writes to one of the three extended registers of the slave

device, as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address, followed by the

write bit (low).

3. The addressed slave device asserts an acknowledge on SDA.

4. The master sends the register address byte. The MSB of

this byte is set to 1 to indicate an extended register write.

The two LSBs indicate which of the three extended registers is

to be written to (see Table 8). All other bits should be set to 0.

5. The slave asserts an acknowledge on SDA.

6. The master sends the extended command byte (refer to

Table 9, Table 10, and Table 11).

7. The slave asserts an acknowledge on SDA.

8. The master asserts a stop condition on SDA to end the

transaction.

SLAVE

ADDRESS

W A

ADDRESS

A P

EXTENDED

COMMAND

BYTE

1 2 3 4 5 6 7 8

05804-009

Figure 21. Write Extended Byte

Table 9, Table 10, and Table 11 provide the details of each

extended register.

Table 8. Extended Register Addresses

A6 A5 A4 A3 A2 A1 A0 Extended Register

0 0 0 0 0 0 1 ALERT_EN

0 0 0 0 0 1 0 ALERT_TH

0 0 0 0 0 1 1 CONTROL

Table 9. ALERT_EN Register Operations

Bit Default Name Function

0 0 EN_ADC_OC1 LSB, enabled if a single ADC conversion on the I channel exceeds the threshold set in the ALERT_TH register.

EN_ADC_OC4

Enabled if four consecutive ADC conversions on the I channel exceed the threshold set in the

ALERT_TH register.

2 0 EN_OC_ALERT Enables the OC_ALERT register. If an overcurrent condition is present compared to the SETV threshold,

the OC_ALERT register captures and latches this condition.

3 0 EN_OFF_ALERT Set this bit high to activate the SWOFF bit (see Table 11).

4 0 CLEAR Clears the OFF_ALERT, OC_ALERT, and ADC_ALERT status bits in the status register. The value of these bits

may immediately change if the source of the alert is not been cleared and the alert function is not disabled.

The CLEAR bit self-clears to 0 after the STATUS register bits have been cleared.

Table 10. ALERT_TH Register Operations

Bit Default Function

7:0 FF The ALERT_TH register sets the current level at which an alert occurs. Defaults to ADC full scale. The ALERT_TH 8-bit value

corresponds to the top eight bits of the current channel data.

Table 11. CONTROL Register Operations

Bit Default Name Function

SWOFF LSB, forces the ALERTB pin to deassert. Can be active only if the EN_OFF_ALERT bit is high (see Table 9).

Data Sheet ADM1191

Rev. C | Page 13 of 16

READ VOLTAGE AND/OR CURRENT DATA BYTES

Depending on how the device is configured, ADM1191 can be

set up to provide information in three ways after a conversion

(or conversions): voltage and current readback, voltage only

readback, and current only readback. See the Write Command

Byte section for more details.

Voltage and Current Readback

The ADM1191 digitizes both voltage and current. Three bytes

are read back in the format shown in Table 12.

Table 12. Voltage and Current Readback

Byte Contents B7 B6 B5 B4 B3 B2 B1 B0

1 Voltage

MSBs

V11 V10 V9 V8 V7 V6 V5 V4

2 Current

MSBs

I11 I10 I9 I8 I7 I6 I5 I4

3 LSBs V3 V2 V1 V0 I3 I2 I1 I0

Voltage Readback

The ADM1191 digitizes voltage only. Two bytes are read back in

the format shown in Table 13.

Table 13. Voltage Only Readback Format

Byte Contents B7 B6 B5 B4 B3 B2 B1 B0

Voltage

MSBs

V11

V10

2 Voltage

LSBs

V3 V2 V1 V0 0 0 0 0

Current Readback

The ADM1191 digitizes current only. Two bytes are read back

in the format shown in Table 14.

Table 14. Current Only Readback Format

Byte Contents B7 B6 B5 B4 B3 B2 B1 B0

1 Current

MSBs

I11 I10 I9 I8 I7 I6 I5 I4

2 Current

LSBs

I3 I2 I1 I0 0 0 0 0

The following series of events occurs when the master receives

three bytes (voltage and current data) from the slave device:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address, followed by the

read bit (high).

3. The addressed slave device asserts an acknowledge on SDA.

4. The master receives the first data byte.

5. The master asserts an acknowledge on SDA.

6. The master receives the second data byte.

7. The master asserts an acknowledge on SDA.

8. The master receives the third data byte.

9. The master asserts a no acknowledge on SDA.

10. The master asserts a stop condition on SDA, and the

transaction ends.

For cases where the master is reading voltage only or current

only, two data bytes are read and Step 7 and Step 8 are not required.

SLAVE

ADDRESS

R A

DATA 1 DATA 2

N PDATA 3A

1 2 3 4 5 6 7 8 9 10

05804-010

Figure 22. Three-Byte Read from ADM1191

SLAVE

ADDRESS

R A

DATA 1

N P

DATA 2

1 2 3 4 5

6 7 8

05804-011

Figure 23. Two-Byte Read from ADM1191

Converting ADC Codes to Voltage and Current Readings

Equation 1 and Equation 2 can be used to convert ADC codes

representing voltage and current from the ADM1191 12-bit ADC

into actual voltage and current values.

Voltage = (V

FULLSCALE

/4096) × Code (1)

where:

FULLSCALE

= 6.65 V (7:2 range) or 26.52 V (14:1 range).

Code is the ADC voltage code read from the device

(Bit V11 to Bit V0).

Current = ((I

FULLSCALE

/4096) × Code)/Sense Resistor (2)

where:

FULLSCALE

= 105.84 mV.

Code is the ADC current code read from the device

(Bit I11 to Bit I0).

Read Status Register

A single register of status data can also be read from the

ADM1191 as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address, followed by the

read bit (high).

3. The addressed slave device asserts an acknowledge on SDA.

4. The master receives the status byte.

5. The master asserts an acknowledge on SDA.

05804-012

SLAVE

ADDRESS

STATUS

BYTE

R A

1 2 3 4 5

Figure 24. Status Read from ADM1191

Table 15 shows the ADM1191 STATUS registers in detail. Note

that Bit 1, Bit 3, and Bit 5 are cleared by writing to Bit 4 (the

CLEAR bit) of the ALERT_EN register.

ADM1191 Data Sheet

Rev. C | Page 14 of 16

Table 15. Status Byte Operations

Bit Name Function

0 ADC_OC An ADC-based overcurrent comparison is detected on the last three conversions.

1 ADC_ALERT An ADC-based overcurrent trip has occurred, causing the alert. Cleared by writing to Bit 4 of the ALERT_EN register.

2 OC An overcurrent condition is present (that is, the output of the current sense amplifier is greater than the voltage on the

SETV input).

3 OC_ALERT An overcurrent condition causes the ALERT block to latch a fault, and the ALERTB output asserts. Cleared by writing to

Bit 4 of the ALERT_EN register.

4 OFF_STATUS Set to 1 by writing to the SWOFF bit of the CONTROL register.

5 OFF_ALERT An alert has been caused by the SWOFF bit. Cleared by writing to Bit 4 of the ALERT_EN register.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

ADM1191-2ARMZ-R7

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Current & Power Monitors & Regulators Digital Pwr Monitor w/AlertB Output IC

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