PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
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SD8_16C16_32x64AG.fm - Rev. E 12/10 EN
1 ©2003, 2004 Micron Technology, Inc. All rights reserved.
128MB (x64, SR), 256MB (x64, DR)
168-PIN SDRAM UDIMM
SYNCHRONOUS
DRAM MODULE
MT8LSDT1664A – 128MB
MT16LSDT3264A – 256MB
For the latest data sheet, please refer to the Micron
®
Web
site: www.micron.com/products/modules
Features
• 168-pin, dual in-line memory module (DIMM)
• PC100- and PC133-compliant
• Utilizes 125 MHz and 133 MHz SDRAM
components
• Unbuffered
• 128MB (16 Meg x 64) and 256MB (32 Meg x 64)
• Single +3.3V power supply
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal SDRAM banks for hiding row access/
precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE and Auto Refresh Modes
• Self Refresh Mode: 64ms, 4,096-cycle refresh
(15.625µs refresh interval)
• LVTTL-compatible inputs and outputs
• Serial Presence-Detect (SPD)
• Gold edge contacts
Figure 1: 168-Pin DIMM (MO-161)
NOTE: 1. Contact Micron for product availability.
Table 1: Timing Parameters
CL = CAS (READ) latency
MODULE
MARKING
CLOCK
FREQUENCY
ACCESS TIME
SETUP
TIME
HOLD
TIMECL = 2 CL = 3
-13E 133 MHz 5.4ns – 1.5 0.8
-133 133 MHz – 5.4ns 1.5 0.8
-10E 100 MHz 9ns 7.5ns 2ns 1ns
Options
Marking
Y
1
• Frequency/CAS Latency
133 MHz/CL = 2 -13E
133 MHz/CL = 3 -133
100 MHz/CL = 2 -10E
•PCB
Standard 1.375in. (34.93mm)
Low-Profile 1.125in. (28.58mm)
1
Standard 1.375in. (34.93mm)
Low Profile 1.125in. (28.58mm)
Table 2: Address Table
128MB 256MB
Refresh Count
4K 4K
Device Banks
4 (BA0, BA1) 4 (BA0, BA1)
Device Configuration
128Mb (16 Meg x 8) 128Mb (16 Meg x 8)
Row Addressing
4K (A0–A11) 4K (A0–A11)
Column Addressing
1K (A0–A9) 1K (A0–A9)
Module Ranks
1 (S0#, S2#) 2 (S0#, S2#; S1#, S3#)
