PDF: 09005aef8137b07b/Source: 09005aef8137b02d Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD8_16C16_32x64AG.fm - Rev. E 12/10 EN
6 ©2003, 2004 Micron Technology, Inc. All rights reserved.
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information
27, 115, 111 RAS#,
CAS#,
WE#
Input
Command Inputs: RAS#, CAS#, and WE# (along with S#) define the command
being entered.
42, 79, 125, 163 CK0–CK3 Input
Clock: CK is driven by the system clock. All SDRAM input signals are sampled on
the positive edge of CK. CK also increments the internal burst counter and
controls the output registers.
63, 128 CKE0,
CKE1
Input
Clock Enable: CKE0 activate (HIGH) and deactivate (LOW) the CK signal.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH
operation (all device banks idle), ACTIVE POWER-DOWN (row ACTIVE in any
device bank) or CLOCK SUSPEND operation (burst access in progress). CKE is
synchronous except after the device enters power-down and self refresh
modes, where CKE becomes asynchronous until after exiting the same mode.
The input buffers, including CK, are disabled during power-down and self
refresh modes, providing low standby power.
30, 45, 114, 129 S0#–S3# Input
Chip Select: S# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when S# is registered HIGH. S# is
considered part of the command code.
28–29, 46–47, 112–
113, 130–131
DQMB0–
DQMB7
Input
Input/Output Mask: DQMB is an input mask signal for write accesses and an
output enable signal for read accesses. Input data is masked when DQMB is
sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z
state (two-clock latency) when DQMB is sampled HIGH during a READ cycle.
39, 122 BA0, BA1 Input
Bank Address: BA0 and BA1 define to which device bank the ACTIVE, READ,
WRITE, or PRECHARGE command is being applied.
33, 34, 35, 36, 37,
38, 117, 118, 119,
120, 121, 123
A0–A11 Input
Address Inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ/WRITE commands, to
select one location out of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether the PRECHARGE
applies to once device bank (A10 LOW, device bank selected by BA0, BA1) or all
device banks (A10 HIGH). The address inputs also provide the op-code during a
MODE REGISTER SET command.
83 SCL Input
Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect
data transfer to and from the module.
165–167 SA0–SA2 Input
Presence-Detect Address Inputs: These pins are used to configure the presence-
detect device.
2–5, 7–11, 13–17,
19–20, 55–58, 60,
65–67, 69–72, 74–
77, 86–89, 91–95,
97–101, 103–104,
139–142, 144,
149–151, 153–156,
158–161
DQ0–
DQ63
Input/
Output
Data I/O: Data bus.
82 SDA Input/
Output
Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer
addresses and data into and data out of the presence-detect portion of the
module.
6, 18, 26, 40, 41,
49, 59, 73, 84, 90,
102, 110, 124, 133,
143, 157, 168
VDD Supply
Power Supply: +3.3V ±0.3V.
