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SD8_16C16_32x64AG.fm - Rev. E 12/10 EN
12 ©2003, 2004 Micron Technology, Inc. All rights reserved.
1. A0–A11provide device row address, and BA0, BA1 determine which device bank is made active.
2. A0–A9 provide device column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW
disables the auto precharge feature; BA0, BA1 determine which device bank is being read from or written to.
3. A10 LOW: BA0, BA1 determine which device bank is being precharged. A10 HIGH: all device banks are precharged and
BA0, BA1 are “Don’t Care.”
4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
6. A0–A11 define the op-code written to the mode register.
7. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
Table 9: SDRAM Commands and DQMB Operation Truth Table
NAME (FUNCTION) CS# RAS# CAS# WE# DQMB ADDR DQ NOTES
XXX X X X
NO OPERATION (NOP)
LHHH X X X
ACTIVE (Select bank and activate row)
L L H H X Bank/Row X 1
READ (Select bank and column, and start READ burst)
LHLHL/H8Bank/ColX 2
WRITE (Select bank and column, and start WRITE burst)
L H L L L/H8 Bank/Col Valid 2
BURST TERMINATE
LHHL X XActive
PRECHARGE (Deactivate row in bank or banks)
LLHL X Code X 3
AUTO refresh or Self Refresh (Enter self refresh mode)
LLLHX X X4, 5
LOAD MODE REGISTER
LLLL XOp-codeX 6
Write Enable/Output Enable
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