1
FN4749.6
HIP6501A
Triple Linear Power Controller with ACPI
Control Interface
The HIP6501A, paired with either the HIP6020 or HIP6021,
simplifies the implementation of ACPI-compliant designs in
microprocessor and computer applications. The IC
integrates two linear controllers and a low-current pass
transistor, as well as the monitoring and control functions
into a 16-pin SOIC package. One linear controller generates
the 3.3V
DUAL
voltage plane from an ATX power supply’s
5VSB output during sleep states (S3, S4/S5), powering the
PCI slots through an external pass transistor, as instructed
by the status of the 3.3V
DUAL
enable pin. An additional pass
transistor is used to switch in the ATX 3.3V output for PCI
operation during S0 and S1 (active) operatingstates. The
second linear controller supplies the computer system’s
2.5V/3.3V memory power through an external pass
transistor in active states. During S3 state, an integrated
pass transistor supplies the 2.5V/3.3V sleep-state power. A
third controller powers up a 5V
DUAL
plane by switching in
the ATX 5V output in active states, or the ATX 5VSB in sleep
states.
The HIP6501A’s operating mode (active-state outputs or
sleep-state outputs) is selectable through two control pins:
S3
and S5. Further control of the logic governing activation
of different power modes is offered through two enabling
pins: EN3VDL
and EN5VDL. In active states, the 3.3V
DUAL
linear regulator uses an external N-Channel pass MOSFET
to connect the output (V
OUT1
) directly to the 3.3V input
supplied by an ATX (or equivalent) power supply, while
incurring minimal losses. In sleep state, the 3.3V
DUAL
output
is supplied from the ATX 5VSB through an NPN transistor,
also external to the controller. Active state power delivery for
the 2.5/3.3V
MEM
output is done through an external NPN
transistor, or an NMOS switch for the 3.3V setting. In sleep
states, conduction on this output is transferred to an internal
pass transistor. The 5V
DUAL
output is powered through two
external MOS transistors. In sleep states, a PMOS (or PNP)
transistor conducts the current from the ATX 5VSB output,
while in active states, current flow is transferred to an NMOS
transistor connected to the ATX 5V output. Similar to the
3.3V
DUAL
output, the operation of the 5V
DUAL
output is
dictated not only by the status of the S3
and S5 pins, but that
of the EN5VDL pin as well.
Features
Provides 3 ACPI-Controlled Voltages
- 5V Active/Sleep (5V
DUAL
)
- 3.3V Active/Sleep (3.3V
DUAL
)
- 2.5V/3.3V Active/Sleep (2.5V
MEM
)
Simple Control Design - No Compensation Required
Excellent Output Voltage Regulation
-3.3V
DUAL
Output: 2.0% Over Temperature; Sleep
States Only
- 2.5V/3.3V Output: 2.0% Over Temperature; Both
Operational States (3.3V setting in sleep only)
Fixed Output Voltages Require No Precision External
Resistors
Small Size
- Small External Component Count
Selectable 2.5V
MEM
Output Voltage Via FAULT/MSEL Pin
- 2.5V for RDRAM Memory
- 3.3V for SDRAM Memory
Under-Voltage Monitoring of All Outputs with Centralized
FAULT Reporting
Adjustable Soft-Start Function Eliminates 5VSB
Perturbations
Pb-Free Available (RoHS Compliant)
Pinout
HIP6501A (SOIC)
TOP VIEW
Ordering Information
PART NUMBER
TEMP.
RANGE (°C) PACKAGE
PKG.
DWG. #
HIP6501ACB 0 to 70 16 Ld SOIC M16.15
HIP6501ACBZ
(Note)
0 to 70 16 Ld SOIC
(Pb-free)
M16.15
HIP6501AEVAL1 Evaluation Board
*Add “-T” suffix to part number for tape and reel packaging.
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish, which
are RoHS compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-
020.
10
11
12
13
14
15
16
7
6
5
4
3
2
1
EN3VDL
3V3DLSB
S3
3V3DL
EN5VDL
5VSB
VSEN2
12V
DLA
SS
FAULT/MSEL
5VDL
S5
DRV2
GND
5VDLSB
9
8
Data Sheet December 30, 2004
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas LLC 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
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2
FN4749.6
December 30, 2004
Block Diagram
S3
5VSB
GND
4.5V/4.0V
EA2
5VSB POR
S5
12V
5VDLSB
+
-
3V3DL
FAULT/MSEL
UV DETECTOR
TO
UV DETECTOR
TO 12V
12V BIAS
EN5VDL
5VDL
EA4
3V3DLSB
SS
UV COMPARATOR
3.75V
DLA
VSEN2
DRV2
EN3VDL
40A
0.2V
MONITOR AND CONTROL
10.8V/9.0V
12V MONITOR
1.265V
MEM VOLTAGE
SELECT COMP
TEMPERATURE
MONITOR
(TMON)
10A
DELAY
+
-
+
-
+
-
+
-
+
-
-
+
FIGURE 1.
HIP6501A
3
FN4749.6
December 30, 2004
Simplified Power System Diagram
Typical Application
+5V
SB
Q3
2.5V
MEM
LINEAR
HIP6501A
+3.3V
IN
+12V
IN
S5
EN5VDL
+5V
IN
3.3V
DUAL
5V
DUAL
CONTROL
Q1
Q4
Q5
Q2
LINEAR
FAULT
S3
EN3VDL
SHUTDOWN
CONTROLLER
LOGIC
CONTROLLER
FIGURE 2.
GND
5VSB
+3.3V
IN
+5V
SB
VSEN2
DRV2
S3
C
OUT2
HIP6501A
12V
+12V
IN
V
OUT2
2.5/3.3V
MEM
Q1
SLP_S3
SLP_S5
S5
V
OUT1
3.3V
DUAL
C
OUT1
+5V
IN
C
OUT3
V
OUT3
5V
DUAL
3V3DL
3V3DLSB
Q2
Q3
Q4
Q5
DLA
5VDLSB
FAULT/MSEL
5VDL
SS
EN5VDL
EN5VDL
EN3VDL
EN3VDL
R
SEL
SHUTDOWN
FAULT
FIGURE 3.
C
SS
HIP6501A

HIP6501ACBZ-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
PMIC Solutions COMPANION CHIP TO HIP60/21 TAPE/REEL
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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