11
FN4749.6
December 30, 2004
capacitance (aluminum electrolytics or tantalum capacitors)
placement is not as critical as the high-frequency capacitor
placement, but having these capacitors close to the load
they serve is preferable.
The only critical small signal component is the soft-start
capacitor, C
SS
. Locate this component close to SS pin of the
control IC and connect to ground through a via placed close
to the capacitor’s ground pad. Minimize any leakage current
paths from SS node, since the internal current source is only
10A.
A multi-layer printed circuit board is recommended. Figure
12 shows the connections of most of the components in the
converter. Note that the individual capacitors each could
represent numerous physical capacitors. Dedicate one solid
layer for a ground plane and make all critical component
ground connections through vias placed as close to the
component as possible. Dedicate another solid layer as a
power plane and break this plane into smaller islands of
common voltage levels. Ideally, the power plane should
support both the input power and output power nodes. Use
copper filled polygons on the top and bottom circuit layers to
create power islands connecting the filtering components
(output capacitors) and the loads. Use the remaining printed
circuit layers for small signal wiring.
Component Selection Guidelines
Output Capacitors Selection
The output capacitors for all outputs should be selected to
allow the output voltage to meet the dynamic regulation
requirements of active state operation (S0, S1). The load
transient for the various microprocessor system’s
components may require high quality capacitors to supply
the high slew rate (di/dt) current demands. Thus, it is
recommended that capacitors C
OUT1
and C
OUT2
should be
selected for transient load regulation.
Also, during the transition between active and sleep states,
there is a short interval of time during which none of the
power pass elements are conducting - during this time the
output capacitors have to supply all the output current. The
output voltage drop during this brief period of time can be
approximated with the following formula:
, where
V
OUT
- output voltage drop
ESR
OUT
- output capacitor bank ESR
I
OUT
- output current during transition
C
OUT
- output capacitor bank capacitance
t
t
- active-to-sleep or sleep-to-active transition time (10s
typical)
Since the output voltage drop is heavily dependent on the
ESR (equivalent series resistance) of the output capacitor
bank, the capacitors should be chosen to maintain the output
voltage above the lowest allowable regulation level.
Input Capacitors Selection
The input capacitors for an HIP6501A application must have
sufficiently low ESR so that the input voltage does not dip
excessively when energy is transferred to the output
capacitors. If the ATX supply does not meet the
specifications, certain imbalances between the ATX’s
outputs and the HIP6501A’s regulation levels could result in
a brisk transfer of energy from the input capacitors to the
supplied outputs. When transiting from active to sleep
states, this phenomena could result in the 5VSB voltage
dropping below the POR level (typically 4.3V) and
temporarily disabling the HIP6501A. The solution to this
potential problem is to use larger input capacitors (on 5VSB)
with a lower total combined ESR.
Transistor Selection/Considerations
The HIP6501A typically requires one P-Channel and two
N-Channel power MOSFETs and two bipolar NPN transistors.
One general requirement for selection of transistors for all
the linear regulators/switching elements is package selection
for efficient removal of heat. The power dissipated in a linear
regulator/switching element is:
Select a package and heatsink that maintains the junction
temperature below the rating with the maximum expected
ambient temperature.
Q1
The active element on the 2.5V/3.3V
MEM
output has
different requirements for each of the two voltage settings. In
2.5V systems utilizing RDRAM (or voltage-compatible)
memory, Q1 must be a bipolar NPN capable of conducting
the maximum required output current and it must have a
minimum current gain (h
fe
) of 100-150 at this current and
0.7V V
CE
. In such systems, the 2.5V output is regulated
from the ATX 3.3V output while in an active state. In 3.3V
systems (SDRAM or compatible) Q1 must be an N-Channel
MOSFET, since the MOSFET serves as a switch during
active states (S0, S1). The main criteria for the selection of
this transistor is output voltage budgeting. The maximum
r
DS(ON)
allowed at highest junction temperature can be
expressed with the following equation:
, where
V
IN MIN
- minimum input voltage
V
OUT MIN
- minimum output voltage allowed
I
OUT MAX
- maximum output current
The gate bias available for this MOSFET is approximately 8V.
V
OUT
I
OUT
ESR
OUT
t
t
C
OUT
------------------+
=
P
LINEAR
I
O
V
IN
V
OUT
–=
r
DS ON MAX
V
IN MIN
V
OUTMIN
–
I
OUT MAX
------------------------------------------------------------=
HIP6501A
