13
FN4749.6
December 30, 2004
HIP6501A Application Circuit
Figure 13 shows an application circuit of an ACPI-compliant
power management system for a microprocessor computer
system. The power supply provides the PCI 3.3V
DUAL
voltage (V
OUT1
), the RDRAM 2.5V
MEM
memory voltage
(V
OUT2
), and the 5V
DUAL
voltage (V
OUT3
) from +3.3V, +5V,
+5VSB, and +12VDC ATX supply outputs. For systems
employing SDRAM memory, replace R1 with 10k and Q1
with an HUF76113SK8. Q4 can also be a PNP, such as an
MMBT2907AL. For detailed information on the circuit,
including a Bill-of-Materials and circuit board description, see
Application Note AN9846.
See Intersil’s web site www.intersil.com for the latest
information.
C6
C5
R1
2x150F
1F
150F
220F
GND
5VSB
+3.3V
IN
+5V
SB
VSEN2
DRV2
S3
C8,9
HIP6501A
12V
+12V
IN
V
OUT2
2.5V
MEM
Q1
S3
S5
S5
V
OUT1
3.3V
DUAL
+5V
IN
C11
V
OUT3
5V
DUAL
3V3DL
3V3DLSB
Q2
Q3
Q4
DLA
5VDLSB
FAULT/MSEL
5VDL
SS
EN5VDL
EN5VDL
EN3VDL
EN3VDL
+
+
C4
1F
C2
1F
C3
220F
+
C10
1F
+
1K
1F
C12
1F
2SD1802
2SD1802
FDV304P
SHUTDOWN
1/2 HUF76113DK8
C7
U1
C13
0.1F
(FROM OPEN-DRAIN N-MOS)
C1
10F
FIGURE 13. TYPICAL HIP6501A APPLICATION CIRCUIT
Q5
1/2 HUF76113DK8
+
HIP6501A
14
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN4749.6
December 30, 2004
HIP6501A
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C A
M
B
S
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45
o
C
H
µ
0.25(0.010) B
M
M
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.053 0.069 1.35 1.75 -
A1 0.004 0.010 0.10 0.25 -
B 0.014 0.019 0.35 0.49 9
C 0.007 0.010 0.19 0.25 -
D 0.386 0.394 9.80 10.00 3
E 0.150 0.157 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H 0.228 0.244 5.80 6.20 -
h 0.010 0.020 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N16 167
0
o
8
o
0
o
8
o
-
Rev. 1 02/02

HIP6501ACBZ-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
PMIC Solutions COMPANION CHIP TO HIP60/21 TAPE/REEL
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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