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85104AGILF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
85104I Data Sheet
©2016 Integrated Device Technology, Inc Revision A January 20, 201610
FIGURE 3C. CLK/nCLK INPUT DRIVEN BY A
3.3V LVPECL DRIVER
FIGURE 3B. CLK/nCLK INPUT DRIVEN BY A
3.3V LVPECL DRIVER
FIGURE 3D. CLK/nCLK INPUT DRIVEN BY A
3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other
differential signals. Both differential signals must meet the V
PP and
V
CMR input requirements. Figures 3A to 3E show interface examples
for the CLK/nCLK input driven by the most common driver types.
The input interfaces suggested here are examples only. Please
FIGURE 3A. CLK/nCLK INPUT DRIVEN BY AN
IDT OPEN EMITTER LVHSTL DRIVER
consult with the vendor of the driver component to confi rm the
driver termination requirements. For example in Figure 3A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
FIGURE 3E. CLK/nCLK INPUT DRIVEN BY A
3.3V HCSL DRIVER
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
85104I Data Sheet
©2016 Integrated Device Technology, Inc Revision A January 20, 201611
RECOMMENDED TERMINATION
Figure 4A is the recommended source termination for
applications where the driver and receiver will be on separate
PCBs. This termination is the standard for PCI Express and
FIGURE 4A. RECOMMENDED TERMINATION
Figure 4B is the recommended termination for applications
where a point-to-point connection can be used. A point-to-point
connection contains both the driver and the receiver on the same
PCB. With a matched termination at the receiver, transmission-
line refl ections will be minimized. In addition, a series resister
FIGURE 4B. RECOMMENDED TERMINATION
(Rs) at the driver offers fl exibility and can help dampen unwanted
refl ections. The optional resister can range from 0Ω to 33Ω.
All traces should be 50Ω impedance single ended or 100Ω
differential.
0-0.2"
PCI Express
L1
L1
1-14"
Driver
Rs
0.5" Max
L3
L4
L2
L2
49.9 +/- 5%
22 to 33 +/-5%
Rt
L3
L4
L5
0.5 - 3.5"
L5
Connector
PCI Express
Add-in Card
PCI Express
0-0.2"
PCI Express
0-0.2"0-18"
L1
L1
Rs
Driver
0.5" Max
L3
L3
L2
L2
49.9 +/- 5%
0 to 33
0 to 33
Rt
HCSL output types. All traces should be 50Ω impedance single
ended or 100Ω differential.
85104I Data Sheet
©2016 Integrated Device Technology, Inc Revision A January 20, 201612
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the 85104I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 85104I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
DD
= 3.3V + 10% = 3.63V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)
MAX
= V
DD_MAX
* I
DD_MAX
= 3.63V * 27mA = 98.01mW
• Power (outputs)
MAX
= 47.3mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 47.3mW = 189.2mW
Total Power
_MAX
(3.63V, with all outputs switching) = 98.01mW + 189.2mW = 287.21mW
2. Junction Temperature.
Junction temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum
recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in Section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
JA
must be used. Assuming no air fl ow
and a multi-layer board, the appropriate value is 91.1°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.287W * 91.1°C/W = 111.1°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow,
and the type of board (multi-layer).
TABLE 6. THERMAL RESISTANCE θ
JA
FOR 20-LEADN TSSOP, FORCED CONVECTION
θ
JA
by Velocity (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 91.1°C/W 86.7°C/W 84.6°C/W
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

85104AGILF

Mfr. #:
Buy 85104AGILF
Manufacturer:
IDT
Description:
Clock Buffer DIFFERENTIAL CLOCK
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