AD7798BRUZ Datasheet AD7799BRUZ-REEL, AD7798BRUZ, AD7799BRUZ | P13-P15

Data Sheet AD7798/AD7799

Rev. B | Page 13 of 28

ON-CHIP REGISTERS

The ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following

descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise stated.

COMMUNICATION REGISTER

RS2, RS1, RS0 = 0, 0, 0

The communication register is an 8-bit, write-only register. All communication to the part must start with a write operation to the

communication register. The data written to the communication register determines whether the next operation is a read or write

operation, and to which register this operation takes place. After the read or write operation is complete, the interface returns to its

default state, where it expects a write operation to the communication register. In situations where the interface sequence is lost, a write

operation of at least 32 serial clock cycles with DIN high returns the ADC to this default state by resetting the entire part. Table 9 outlines

the bit designations for the communication register. CR0 through CR7 indicate the bit location, with CR denoting that the bits are in the

communication register. CR7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default

status of that bit.

CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0

WEN

(0) R/

(0) RS2(0) RS1(0) RS0(0) CREAD(0) 0(0) 0(0)

Table 9. Communication Register Bit Designations

Bit Location Bit Name Description

CR7

WEN

Write Enable Bit. A 0 must be written to this bit so that the write to the communication register occurs.

If a 1 is the first bit written, the part does not clock subsequent bits into the register. It stays at this bit

location until a 0 is written to this bit. Once a 0 is written to the

WEN

bit, the next seven bits are loaded

to the communication register.

CR6 R/

Read/

Write

Bit. A 0 in this bit location indicates that the next operation is a write to a specified register.

A 1 in this position indicates that the next operation is a read from the designated register.

CR5 to CR3 RS2 to RS0 Register Address Bits. These bits are used to select the register during the serial interface communication.

See Table 10.

CR2 CREAD Continuous Read of the Data Register Bit. When this bit is set to 1 and the data register is selected, the

serial interface is configured so that the data register can be continuously read, that is, the contents of

the data register are placed on the DOUT pin automatically when the SCLK pulses are applied after the

RDY

pin goes low to indicate that a conversion is complete. The communication register does not have

to be written to for data reads. To enable continuous read mode, the instruction 01011100 must be

written to the communication register. To exit the continuous read mode, the instruction 01011000

must be written to the communication register while the

RDY

pin is low. While in continuous read mode,

the ADC monitors activity on the DIN line for the instruction to exit continuous read mode. Additionally,

a reset occurs if 32 consecutive 1s are seen on DIN. Therefore, DIN should be held low in continuous read

mode until an instruction is to be written to the device.

CR1 to CR0 0 These bits must be programmed to Logic 0 for correct operation.

Table 10. Register Selection

RS2 RS1 RS0 Register Register Size

0 0 0 Communication register during a write operation 8 bits

0 0 0 Status register during a read operation 8 bits

0 0 1 Mode register 16 bits

0 1 0 Configuration register 16 bits

0 1 1 Data register 16 bits (AD7798)/24 bits (AD7799)

1 0 0 ID register 8 bits

1 0 1 IO register 8 bits

1 1 0 Offset register 16 bits (AD7798)/24 bits (AD7799)

1 1 1 Full-scale register 16 bits (AD7798)/24 bits (AD7799)

AD7798/AD7799 Data Sheet

Rev. B | Page 14 of 28

STATUS REGISTER

RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80 (AD7798)/0x88 (AD7799)

The status register is an 8-bit, read-only register. To access the status register, the user must write to the communication register, select the

next operation to be a read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 11 outlines the bit designations for the status register. SR0

through SR7 indicate the bit locations, with SR denoting that the bits are in the status register. SR7 denotes the first bit of the data stream.

The number in parentheses indicates the power-on/reset default status of the bit.

SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0

RDY

(1) ERR(0) NOREF(0) 0(0) 0/1 CH2(0) CH1(0) CH0(0)

Table 11. Status Register Bit Designations

Bit Location Bit Name Description

SR7

RDY

Ready Bit. Cleared when data is written to the data register. Set after the data register is read or after a period

of time before the data register is updated with a new conversion result to indicate to the user not to read the

conversion data. It is also set when the part is placed in power-down mode. The end of a conversion is

indicated by the DOUT/

RDY

pin. This pin can be used as an alternative to the status register for monitoring

the ADC for conversion data.

SR6 ERR Error Bit. This bit is written to at the same time as the

RDY

bit. Set to indicate that the result written to the

data register is clamped to all 0s or all 1s. Error sources include overrange and underrange. Cleared by a write

operation to start a conversion.

SR5 NOREF No Reference Bit. Set to indicate that the reference (REFIN) is at a voltage below a specified threshold. When

NOREF is set, conversion results are clamped to all 1s. Cleared to indicate that a valid reference is applied to

the reference pins. The NOREF bit is enabled by setting the REF_DET bit in the configuration register to 1.

SR4 0 This bit is automatically cleared.

SR3 0/1 This bit is automatically cleared on the AD7798 and automatically set on the AD7799.

SR2 to SR0 CH2 to CH0 These bits indicate which channel is being converted by the ADC.

MODE REGISTER

RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x000A

The mode register is a 16-bit register from which data can be read or to which data can be written. This register is used to select the

operating mode, update rate, and low-side power switch. Table 12 outlines the bit designations for the mode register. MR0 through MR15

indicate the bit locations, with MR denoting that the bits are in the mode register. MR15 denotes the first bit of the data stream. The

number in parentheses indicates the power-on/reset default status of that bit. A write to the mode register resets the modulator and filter

and sets the

RDY

bit.

MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8

MD2(0) MD1(0) MD0(0) PSW(0) 0(0) 0(0) 0(0) 0(0)

MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0

0(0) 0(0) 0(0) 0(0) FS3(1) FS2(0) FS1(1) FS0(0)

Table 12. Mode Register Bit Designations

Bit Location Bit Name Description

MR15 to MR13 MD2 to MD0 Mode Select Bits. These bits select the operational mode of the AD7798/AD7799 (see Table 13).

MR12 PSW Power Switch Control Bit. Set by user to close the power switch PSW to GND. The power switch can

sink up to 30 mA. Cleared by user to open the power switch. When the ADC is placed in power-down

mode, the power switch is opened.

MR11 to MR4 0 These bits must be programmed with a Logic 0 for correct operation.

MR3 to MR0 FS3 to FS0 Filter Update Rate Select Bits (see Table 14).

Data Sheet AD7798/AD7799

Rev. B | Page 15 of 28

Table 13. Operating Modes

MD2 MD1 MD0 Mode

0 0 0 Continuous-Conversion Mode (Default). In continuous-conversion mode, the ADC continuously performs conversions

and places the result in the data register.

RDY

goes low when a conversion is complete. After power-on, a channel

change, or a write to the mode, configuration, or IO registers, the first conversion is available after a period of 2/f

ADC

and subsequent conversions are available at a frequency of f

ADC

0 0 1 Single-Conversion Mode. When single-conversion mode is selected, the ADC powers up and performs a single

conversion. The oscillator requires 1 ms to power up and settle. The ADC then performs the conversion, which takes

a time of 2/f

ADC

. The conversion result is placed in the data register,

RDY

goes low, and the ADC returns to power-

down mode. The conversion remains in the data register and

RDY

remains active (low) until the data is read or

another conversion is performed.

0 1 0 Idle Mode. In idle mode, the ADC filter and modulator are held in a reset state, although the modulator clocks are

still provided.

Power-Down Mode. In this mode, all AD7798/AD7799 circuitry is powered down, including the burnout currents.

1 0 0 Internal Zero-Scale Calibration. An internal short is automatically connected to the enabled channel. A calibration

takes two conversion cycles to complete.

RDY

goes high when the calibration is initiated and returns low when the

calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is

placed in the offset register of the selected channel.

1 0 1 Internal Full-Scale Calibration. A full-scale input voltage is automatically connected to the selected analog input for

this calibration. When the gain equals 1, a calibration takes t

wo conversion cycles to complete. For higher gains, four

conversion cycles are required to perform the full-scale calibration.

RDY

goes high when the calibration is initiated

and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The

measured full-scale coefficient is placed in the full-scale register of the selected channel. Internal full-scale

calibrations cannot be performed when the gain equals 128. The ADC is factory-calibrated at a gain of 128 and this

factory-generated value is placed in the full-scale register on power up and when the gain is set to 128. With this

gain setting, a system full-scale calibration can be performed. To minimize the full-scale error, a full-scale calibration

is required each time the gain of a channel is changed.

1 1 0 System Zero-Scale Calibration. Users should connect the system zero-scale input to the channel input pins as

selected by the CH2 to CH0 bits. A system offset calibration takes two conversion cycles to complete.

RDY

goes high

when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode

following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. A

zero-scale calibration is required each time the gain of a channel is changed.

1 1 1 System Full-Scale Calibration. Users should connect the system full-scale input to the channel input pins, as selected

by the CH2 to CH0 bits. A calibration takes two conversion cycles to complete.

RDY

goes high when the calibration

is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration.

The measured full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration

is required each time the gain of a channel is changed.

Table 14. Update Rates Available

FS3 FS2 FS1 FS0 f

ADC

(Hz) t

SETTLE

(ms) Rejection @ 50 Hz/60 Hz

0 0 0 0 Reserved

0 0 0 1 470 4

0 0 1 0 242 8

0 0 1 1 123 16

0 1 0 0 62 32

0 1 0 1 50 40

0 1 1 0 39 48

33.2

1 0 0 0 19.6 101 90 dB (60 Hz only)

1 0 0 1 16.7 120 80 dB (50 Hz only)

1 0 1 0 16.7 120 65 dB

1 0 1 1 12.5 160 66 dB

1 1 0 0 10 200 69 dB

8.33

240

70 dB

1 1 1 0 6.25 320 72 dB

1 1 1 1 4.17 480 74 dB

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

AD7798BRUZ

Mfr. #:

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Analog to Digital Converters - ADC 3-Ch 16-Bit Low Noise Low Power

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AD7798BRUZ

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