AD7798/AD7799 Data Sheet
Rev. B | Page 16 of 28
CONFIGURATION REGISTER
RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x0710
The configuration register is a 16-bit register from which data can be read or to which data can be written. This register is used to
configure the ADC for unipolar or bipolar mode, to enable or disable the buffer, to enable or disable the burnout currents, to select the
gain, and to select the analog input channel. Table 15 outlines the bit designations for the filter register. CON0 through CON15 indicate
the bit locations, with CON denoting that the bits are in the configuration register. CON15 denotes the first bit of the data stream. The
number in parentheses indicates the power-on/reset default status of the bit.
CON15 CON14 CON13 CON12 CON11 CON10 CON9 CON8
0(0) 0(0) BO(0) U/
B
(0) 0(0) G2(1) G1(1) G0(1)
CON7 CON6 CON5 CON4 CON3 CON2 CON1 CON0
0(0) 0(0) REF_DET(0) BUF(1) 0(0) CH2(0) CH1(0) CH0(0)
Table 15. Configuration Register Bit Designations
Bit Location Bit Name Description
CON15 to CON14
0
These bits must be programmed with a Logic 0 for correct operation.
CON13 BO Burnout Current Enable Bit. When this bit is set to 1 by the user, the 100 nA current sources in the signal path
are enabled. When BO = 0, the burnout currents are disabled. The burnout currents can be enabled only when
the buffer or in-amp is active.
CON12
U/
B
Unipolar/Bipolar Bit. Set by the user to enable unipolar coding, that is, zero differential input results in
0x000000 output, and a full-scale differential input results in 0xFFFFFF output. Cleared by the user to enable
bipolar coding. Negative full-scale differential input results in an output code of 0x000000, zero differential
input results in an output code of 0x800000, and a positive full-scale differential input results in an output
code of 0xFFFFFF.
CON11 0 This bit must be programmed with a Logic 0 for correct operation.
CON10 to CON8 G2 to G0 Gain Select Bits. Written to by the user to select the ADC input range as follows:
G2 G1 G0 Gain ADC Input Range (2.5 V Reference)
0 0 0 1 (in-amp not used) 2.5 V
0 0 1 2 (in-amp not used) 1.25 V
0 1 0 4 625 mV
0 1 1 8 312.5 mV
1 0 0 16 156.2 mV
1 0 1 32 78.125 mV
1 1 0 64 39.06 mV
1 1 1 128 19.53 mV
CON7 to CON6 0 These bits must be programmed with a Logic 0 for correct operation.
CON5 REF_DET Enables the reference detect function. When REF_DET is set, the NOREF bit in the status register indicates
when the external reference being used by the ADC is open circuit or less than 0.5 V. When cleared, the
reference detect function is disabled.
CON4 BUF Configures the ADC for buffered or unbuffered modes. If BUF is cleared, the ADC operates in unbuffered
mode, lowering the power consumption of the device. If BUF is set, the ADC operates in buffered mode,
allowing the user to place source impedances on the front end without contributing gain errors to the system.
The buffer can be disabled when the gain equals 1 or 2. For higher gains, the buffer is automatically enabled.
With the buffer disabled, the voltage on the analog input pins can range from 30 mV below GND to 30 mV
above AV
DD
. When the buffer is enabled, it requires some headroom; therefore, the voltage on any input pin
must be limited to 100 mV within the power supply rails.
CON3 0 This bit must be programmed with a Logic 0 for correct operation.
CON2 to CON0 CH2 to CH0 Channel Select Bits. Written to by the user to select the active analog input channel to the ADC as follows:
CH2 CH1 CH0 Channel Calibration Pair
0 0 0 AIN1(+) AIN1() 0
0 0 1 AIN2(+) AIN2() 1
0 1 0 AIN3(+) AIN3() 2
0 1 1 AIN1() AIN1(–) 0
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 AV
DD
monitor Automatically selects gain = 1/6 and internal
reference = 1.17 V
Data Sheet AD7798/AD7799
Rev. B | Page 17 of 28
DATA REGISTER
RS2, RS1, RS0 = 0, 1, 1; Power-On/Reset = 0x0000(00)
The conversion result from the ADC is stored in the data register. This is a read-only register. Upon completion of a read operation from
this register, the
RDY
bit and DOUT/
RDY
pin are set.
ID REGISTER
RS2, RS1, RS0 = 1, 0, 0; Power-On/Reset = 0xX8 (AD7798)/0xX9 (AD7799)
The identification number for the AD7798/AD7799 is stored in the ID register. This is a read-only register.
IO REGISTER
RS2, RS1, RS0 = 1, 0, 1; Power-On/Reset = 0x00
The IO register is an 8-bit register from which data can be read or to which data can be written. This register is used to select the function
of the AIN3(+)/AIN3() pins. Table 16 outlines the bit designations for the IO register. IO0 through IO7 indicate the bit locations, with
IO denoting that the bits are in the IO register. IO7 denotes the first bit of the data stream. The number in parentheses indicates the
power-on/reset default status of that bit.
IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0
0(0) IOEN(0) IO2DAT(0) IO1DAT(0) 0(0) 0(0) 0(0) 0(0)
Table 16. IO Register Bit Designations
Bit Location Bit Name Description
IO7 0 This bit must be programmed with a Logic 0 for correct operation.
IO6 IOEN Configures the pins AIN3(+)/P1 and AIN3(−)/P2 as analog input pins or digital output pins. When
this bit is set, the pins are configured as Digital Output Pins P1 and P2. When this bit is cleared,
these pins are configured as analog input pins AIN3(+) and AIN3(−).
IO5, IO4
IO2DAT, IO1DAT
P1/P2 Data. When IOEN is set, the data for the Digital Output Pins P1 and P2 is written to Bit IO1DAT
and Bit IO2DAT.
IO3 to IO0 0 These bits must be programmed with a Logic 0 for correct operation.
OFFSET REGISTER
RS2, RS1, RS0 = 1, 1, 0; Power-On/Reset = 0x8000(AD7798)/0x800000 (AD7799)
Each analog input channel has a dedicated offset register that holds the offset calibration coefficient for the channel. This register is
16 bits wide on the AD7798 and 24 bits wide on the AD7799, and its power-on/reset value is 8000(00) hex. The offset register is used in
conjunction with its associated full-scale register to form a register pair. The power-on/reset value is automatically overwritten if an
internal or system zero-scale calibration is initiated by the user. The offset register is a read/write register. However, the AD7798/AD7799
must be in idle mode or power-down mode when writing to the offset register.
FULL-SCALE REGISTER
RS2, RS1, RS0 = 1, 1, 1; Power-On/Reset = 0x5XXX (AD7798)/0x5XXX00 (AD7799)
The full-scale register is a 16-bit register on the AD7798 and a 24-bit register on the AD7799. The full-scale register holds the full-scale
calibration coefficient for the ADC. The AD7798/AD7799 has three full-scale registers, with each channel having a dedicated full-scale
register. The full-scale registers are read/write registers. However, when writing to the full-scale registers, users must place the ADC in
power-down mode or idle mode. Upon power-on, these registers are configured with factory-calibrated, full-scale calibration coefficients,
with the calibration performed at gain = 128, the default gain setting. The default value is automatically overwritten if an internal or
system full-scale calibration is initiated by the user, or the full-scale register is written to.
AD7798/AD7799 Data Sheet
Rev. B | Page 18 of 28
ADC CIRCUIT INFORMATION
DOUT/RDY
DIN
SCLK
CS
DV
DD
SERIAL
INTERFACE
AND
CONTROL
LOGIC
Σ-Δ
ADC
AD7798/AD7799
AIN2(+)
AIN2(–)
AIN1(+)
AIN1(–)
AV
DD
GND
MUX
INTERNAL
CLOCK
GND
AV
DD
REFIN(–)
REFIN(+)
PSW
IN-AMP
REFERENCE
DETECT
IN+
IN–
OUT–
OUT+
AV
DD
04856-012
Figure 11. Basic Connection Diagram
OVERVIEW
The AD7798/AD7799 are low power ADCs that each incorporate
a ∑-∆ modulator, a buffer, an in-amp, and on-chip digital filtering
intended for the measurement of wide dynamic range, low
frequency signals, such as those in pressure transducers and
weigh scales.
Each part has three differential inputs that can be buffered or
unbuffered. The reference is provided by an external reference
source. Figure 11 shows the basic connections required to
operate the parts.
The output rate of the AD7798/AD7799 (f
ADC
) is user-program-
mable. The allowable update rates, along with the corresponding
settling times, are listed in Table 14. Normal mode rejection is
the major function of the digital filter. Simultaneous 50 Hz and
60 Hz rejection is optimized when the update rate equals 16.7 Hz
or less, because notches are placed at both 50 Hz and 60 Hz with
these update rates (see Figure 13).
The AD7798/AD7799 use slightly different filter types,
depending on the output update rate, so that the rejection of
quantization noise and device noise is optimized. When the
update rate ranges from 4.17 Hz to 12.5 Hz, a sinc3 filter, along
with an averaging filter, is used. When the update rate ranges
from 16.7 Hz to 39 Hz, a modified sinc3 filter is used. This filter
gives simultaneous 50 Hz and 60 Hz rejection when the update
rate equals 16.7 Hz. A sinc4 filter is used when the update rate
ranges from 50 Hz to 242 Hz. Finally, an integrate-only filter is
used when the update rate equals 470 Hz. Figure 12 through
Figure 15 show the frequency responses of the different filter
types for a few of the update rates.
0
–20
–40
60
–80
–100
0
120100
8060
4020
04856-013
FREQUENCY (Hz)
(dB)
Figure 12. Filter Profile with Update Rate = 4.17 Hz
0
–20
–40
–60
–80
–100
0 200180160140120100806040
20
04856-014
FREQUENCY (Hz)
(dB)
Figure 13. Filter Profile with Update Rate = 16.7 Hz

AD7798BRUZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 3-Ch 16-Bit Low Noise Low Power
Lifecycle:
New from this manufacturer.
Delivery:
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