HMC7950 Data Sheet
Rev. 0 | Page 12 of 16
THEORY OF OPERATION
The HMC7950 is a GaAs, pHEMT, MMIC low noise amplifier.
Its basic architecture is that of a single-supply, biased cascode
distributed amplifier with an integrated RF choke for the drain.
The cascode distributed architecture uses a fundamental cell
consisting of a stack of two field effect transistors (FETs) with
the source of the upper FET connected to the drain of the lower
FET. The fundamental cell is then duplicated several times, with
a transmission line feeding the RFIN signal to the gates of the
lower FETs and a separate transmission line interconnecting the
drains of the upper FETs and routing the amplified signal to the
RFOUT pin. Additional circuit design techniques around each
cell optimize the overall performance for broadband operation.
The major benefit of this architecture is that high performance
is maintained across a bandwidth far greater than a single
instance of the fundamental cell can provide. A simplified
schematic of this architecture is shown in Figure 37.
Although the gate bias voltages of the upper FETs are set internally
by a resistive voltage divider connected to V
DD
, the V
GG
2 pin
provides the user with an optional means of changing the gate
bias of the upper FETs. Application of a voltage to V
GG
2 allows
the user to change the voltage output by the resistive divider,
altering the gate bias of the upper FETs and thus changing the
gain. Application of V
GG
2 voltages across the range of −2.0 V to
+2.6 V affects gain changes of approximately 30 dB, depending
on the frequency. Increasing the voltage applied to V
GG
2 increases
the gain, whereas decreasing the voltage decreases the gain. For
V
DD
= 5.0 V (nominal), the resulting V
GG
2 open circuit voltage
is approximately 2.2 V.
Figure 37. Architecture and Simplified Schematic
V
GG
2
V
DD
TRANSMISSION
LINE
TRANSMISSION
LINE
R
FOU
T
RFI
N
15412-036
