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a
AD6600
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2000
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Dual IF Inputs, 70 MHz–250 MHz
Diversity or Two Independent IF Signals
Separate Attenuation Paths
Oversample RF Channels
20 MSPS on a Single Carrier
10 MSPS/Channel in Diversity Mode
Total Signal Range 90+ dB
30 dB from Automatic Gain-Ranging (AGC)
60 dB from A/D Converter
Range >100 dB After Processing Gain
Digital Outputs
11-Bit ADC Word
3-Bit RSSI Word
2 Clock, A/B Indicator
Single 5 V Power Supply
Output DVCC 3.3 V or 5 V
775 mW Power Dissipation
APPLICATIONS
Communications Receivers
PCS/Cellular Base Stations
GSM, CDMA, TDMA
Wireless Local Loop, Fixed Access
PRODUCT DESCRIPTION
The AD6600 mixed-signal receiver chip directly samples signals
at analog input frequencies up to 250 MHz. The device includes
two input channels, each with 1 GHz input amplifiers and
30 dB of automatic gain-ranging circuitry. Both channels are
sampled with a 450 MHz track-and-hold followed by an 11-bit,
20 MSPS analog-to-digital converter. Digital RSSI outputs, an
A/B channel indicator, a 2× Clock output, references, and con-
trol circuitry are all on-chip. Digital output signals are two’s
complement, CMOS-compatible and interface directly to
3.3 V or 5 V digital processing chips.
The primary use for the dual analog input structure is sampling
both antennas in a two-antenna diversity receiver. However,
Channels A and B may also be used to sample two independent
IF signals. Diversity, or dual-channel mode, is limited to 10 MSPS
per channel. In single-channel mode, the full clock rate of
20 MSPS may be applied to a single carrier.
The AD6600 may be used as a stand-alone sampling chip, or it
may be combined with the AD6620 Digital Receive Signal Pro-
cessor. The AD6620 provides 10 dB–25 dB of additional pro-
cessing gain before passing data to a fixed- or floating-point DSP.
Driving the AD6600 is simplified by using the AD6630 differen-
tial IF amplifier. The AD6630 is easily matched to inexpensive
SAW filters from 70 MHz to 250 MHz.
Designed specifically for cellular/PCS receivers, the AD6600
supports GSM, IS-136, CDMA and Wireless LANs, as well as
proprietary air interfaces used in WLL/fixed-access systems.
Units are available in plastic, surface-mount packages (44-lead
LQFP) and specified over the industrial temperature range
(–40°C to +85°C).
Dual Channel, Gain-Ranging
ADC with RSSI
GAIN
A/D
CONVERTER
TIMING
ENCODE
SELECT GAIN
+12, +18dB
ENCODE
FLT FLT
NOISE FILTER
RESONANT
PORT
630
RSSI
3
TWO'S
COMPLEMENT
11
AB_OUT
D10–D0
RSSI [2:0]
CLK2
DVCCENCENCGNDAVCCB_SELA_SEL
ANALOG MUX
GAIN
GAIN
RSSI
3
0dB, –12dB, –24dB
ATTEN
ATTEN
0dB, –12dB, –24dB
DETECT
PEAK
SET
RSSI
AIN
AIN
BIN
BIN
AD6600
AD6600* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
DOCUMENTATION
Application Notes
AN-302: Exploit Digital Advantages in an SSB Receiver
AN-502: Designing A Superheterodyne Receiver Using an
IF Sampling Diversity Chipset
AN-835: Understanding High Speed ADC Testing and
Evaluation
AN-851: A WiMax Double Downconversion IF Sampling
Receiver Design
Data Sheet
AD6600: Dual Channel, Gain-Ranging ADC With RSSI Data
Sheet
Product Highlight
Introducing Digital Up/Down Converters: VersaCOMM™
Reconfigurable Digital Converters
REFERENCE MATERIALS
Technical Articles
Basics of Designing a Digital Radio Receiver (Radio 101)
Correlating High-Speed ADC Performance to Multicarrier
3G Requirements
Designing a Super-Heterodyne Multi-Channel Digital
Receiver
Digital Up/Down Converters: VersaCOMM™ White Paper
DNL and Some of its Effects on Converter Performance
MS-2210: Designing Power Supplies for High Speed ADC
Smart Partitioning Eyes 3G Basestation
DESIGN RESOURCES
AD6600 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
View all AD6600 EngineerZone Discussions.
SAMPLE AND BUY
Visit the product page to see pricing options.
TECHNICAL SUPPORT
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number.
DOCUMENT FEEDBACK
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AD6600–SPECIFICATIONS
DC SPECIFICATIONS
Test AD6600AST
Parameter Temp Level Min Typ Max Unit
ANALOG INPUTS (AIN, AIN/BIN, BIN)
Differential Analog Input Voltage Range
1
Full V 2.0 V p-p
Differential Analog Input Resistance
2
Full IV 160 200 240
Differential Analog Input Capacitance 25°C V 1.5 pF
PEAK DETECTOR (Internal), RSSI
Resolution 3 Bits
RSSI Gain Step Full V 6 dB
RSSI Hysteresis
3
Full V 6 dB
RESONANT PORT (FLT, FLT)
Differential Port Resistance Full V 630
Differential Port Capacitance Full V 1.75 pF
A/D CONVERTER
Resolution Full IV 11 Bits
ENCODE INPUTS (ENC, ENC)
Differential Input Voltage (AC-Coupled)
4
Full IV 0.4 V p-p
Differential Input Resistance 25°CV 11 k
Differential Input Capacitance 25°C V 2.5 pF
A/B MODE INPUTS (A_SEL, B_SEL)
5
Input High Voltage Range Full IV 4.75 5.25 V
Input Low Voltage Range Full IV 0.0 0.5 V
POWER SUPPLY
Supply Voltages
AVCC Full II 4.75 5.0 5.25 V
DVCC Full IV 3.0 3.3 5.25 V
Supply Current
I
AVCC
(AVCC = 5.0 V) Full II 145 182 mA
I
DVCC
(DVCC = 3.3 V) Full II 15 20 mA
POWER CONSUMPTION
6
Full II 775 976 mW
NOTES
1
Analog Input Range is a function of input frequency. See ac specifications for 70 MHz–250 MHz inputs.
2
Analog Input Impedance is a function of input frequency. See ac specifications for 70 MHz–450 MHz inputs.
3
Six dB of digital hysteresis is used to eliminate level uncertainty at the RSSI threshold points due to noise and amplitude variations.
4
Encode inputs should be ac-coupled and driven differentially. See Encoding the AD6600 for details.
5
A_SEL and B_SEL should be tied directly to ground or AVCC.
6
Maximum power consumption is computed as maximum current at nominal supplies.
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
Test AD6600AST
Parameter Temp Level Min Typ Max Unit
LOGIC OUTPUTS (D10–D0, AB_OUT, RSSI2–0)
1
Logic Compatibility CMOS
Logic “1” Voltage (DVCC = 3.3 V) Full II 2.8 DVCC – 0.2 V
Logic “0” Voltage (DVCC = 3.3 V) Full II 0.2 0.5 V
Logic “1” Voltage (DVCC = 5.0 V) Full IV 4.0 DVCC – 0.35 V
Logic “0” Voltage (DVCC = 5.0 V) Full IV 0.35 0.5 V
Output Coding (D10–D0) Two’s Complement
CLK2× OUTPUT
1, 2
Logic “1” Voltage (DVCC = 3.3 V) Full II 2.8 DVCC – 0.2 V
Logic “0” Voltage (DVCC = 3.3 V) Full II 0.2 0.5 V
Logic “1” Voltage (DVCC = 5.0 V) Full IV 4.0 DVCC – 0.3 V
Logic “0” Voltage (DVCC = 5.0 V) Full IV 0.35 0.5 V
NOTES
1
Digital output load is one LCX gate.
2
CLK2× output voltage levels, high and low, tested at switching rate of 10 MHz.
Specifications subject to change without notice.
(AVCC = 5 V, DVCC = 3.3 V; T
MIN
= –40C, T
MAX
= +85C unless otherwise noted.)
(AVCC = 5 V, DVCC = 3.3 V; T
MIN
= –40C, T
MAX
= +85C unless otherwise noted.)

AD6600ASTZ-REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC Diversity Receiver Chipset
Lifecycle:
New from this manufacturer.
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