REV. 0 –9
AD6600
PIN FUNCTION DESCRIPTIONS
Pin Number Name Function
1, 33 DVCC Digital VCC for Digital Outputs. Can be 3.3 V.
2, 5, 13, 19, 21, 24, 30, 32 GND Ground.
3 C1 Internal Bias Point. Bypass by 0.01 µF to GND.
4, 14, 15, 18, 20, 25, 31 AVCC 5 V Power Supply.
6–8 RSSI[2:0] RSSI Digital Output Bits.
9, 10 B_SEL, A_SEL Mode Select Pins for Analog Input Channel A and B Sampling.
11 AIN True Analog Input Channel A.
12 AIN Complementary Analog Input Channel A.
16, 17 FLT, FLT Resonant Filter Pins for External LC Noise Filter.
22 BIN Complementary Analog Input Channel B.
23 BIN True Analog Input Channel B.
26 ENC Complementary Encode Input.
27 ENC True Encode Input.
28 CLK2× 2× Clock Output Used for Clocking Digital Filter Chips.
29 AB_OUT Digital Output Flag Indicating Whether Output Is Input A (High) or B (Low).
34 D0 Digital Data Output Bit (Least Significant Bit)*.
35–43 D1–D9 Digital Data Output Bits*.
44 D10 Digital Data Output Bit (Most Significant Bit)*.
*Digital Outputs (D10:D0) in Two’s Complement Format.
PIN CONFIGURATION
3
4
5
6
7
1
2
10
11
8
9
40 39 3841424344 36 35 3437
29
30
31
32
33
27
28
25
26
23
24
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
12
13
14 15 16 17 18 19
20
21 22
DVCC
GND
AVCC
GND
AB_OUT
CLK2
ENC
AD6600
ENC
AVCC
GND
BIN
GND
D10 (MSB)
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
AVCC
GND
BIN
FLT
AIN
GND
AVCC
AVCC
FLT
AVCC
DVCC
GND
C1
AVCC
GND
RSSI2
RSSI1
RSSI0
B_SEL
A_SEL
AIN
REV. 0
AD6600
–10–
DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB. The bandwidth is determined by the internal
track-and-hold when the filter node is resonated.
Aperture Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input-
is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Attenuator 3OIP
The third order intercept point of the front end of the AD6600.
It is the point at which the third order products would theoreti-
cally intercept the input signal level if the input level could increase
without bounds. This is measured using the ADC within the
AD6600 while the input is stimulated with dual tones in the
minimum attenuation (i.e., maximum gain) range.
Channel Isolation
The amount of signal leakage from one channel to the next
when one channel is driven with a full-scale input, and the other
channel is swept from –20 dBFS to –90 dBFS with a frequency
offset. The leakage is measured on the side with the smaller signal.
Differential Analog Input Resistance, Differential Analog
Input Capacitance and Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the capaci-
tance and differential input impedances are measured with a
network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to the
converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin and
subtracting the voltage from the other pin, which is 180 degrees
out of phase. Peak-to-peak differential is computed by rotating
the inputs phase 180 degrees and taking the peak measurement
again. The difference is then computed between both peak
measurements.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Differential Resonant Port Resistance
The resistance shunted across the resonant port (nominally
630 ). Used to determine the filter bandwidth and gain of
that stage.
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in logic “1” state to achieve rated
performance; pulsewidth low is the minimum time ENCODE
pulse should be left in low state. See timing implications of
changing t
ENCH
in text. At a given clock rate, these specifications
define an acceptable Encode duty cycle.
Full-Scale Gain Tolerance
Unit-to-unit variation in full-scale input power.
Full-Scale Input Power
Expressed in dBm. Computed using the following equation:
Power
V
Z
FULL SCALE
FULL SCALE rms
INPUT
=
10
0 001
2
log
.
Gain Matching (Input A:B)
Variation in full-scale power between A and B inputs.
Harmonic Distortion, 2nd
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Harmonic Distortion, 3rd
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a best straight line
determined by a least square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal fre-
quency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Noise (For Any Range Within the ADC)
VZ
NOISE
FS SNR Signal
dBm dBc dBFS
×
−−
0 001 10
10
.
where:
Z is the input impedance,
FS is the full-scale of the device for the frequency in question,
SNR is the value for the particular input level,
Signal is the signal level within the ADC reported in dB below
full scale. This value includes both thermal and quanti-
zation noise.
Range-Range Gain Tolerance
The gain error in the RSSI attenuator ladder from one range to
the next.
Range-Range Phase Tolerance
The phase error in the RSSI attenuator ladder from one range
to the next.
Differential Resonant Port Capacitance
The capacitance between the two resonant pins. Used to deter-
mine filter bandwidth and resonant frequency.
REV. 0
AD6600
–11–
RSSI Gain Step
The input amplitude span between taps of the RSSI (received
signal strength) attenuator ladder. Ideally each stage should
span 6 dB of input power.
RSSI Hysteresis
The amount of movement in the RSSI switch points, depending
on the direction of approach. Hysteresis prevents unnecessary
RSSI toggling when input signal power is near a threshold.
Signal-to-Noise Ratio (Without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, excluding the first five harmonics and dc.
Worst Other Spur
The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonic) reported in dBc.
AD6600 TRANSFER FUNCTION
AIN LEVEL dBFS
60
24
0
100
0
90
SNR dB
80 70 60 50 40 30 20 10
54
30
18
6
42
36
12
48
Figure 1. SNR vs. Input Power

AD6600ASTZ-REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC Diversity Receiver Chipset
Lifecycle:
New from this manufacturer.
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