REV. 0
–4–
AD6600–SPECIFICATIONS
TIMING REQUIREMENTS AND SWITCHING SPECIFICATIONS
1, 2
(AVCC = 5 V, DVCC = 3.3 V; ENC and ENC = 20 MSPS, Duty Cycle = 50%; T
MIN
= –40C, T
MAX
= +85C unless otherwise noted.)
Test AD6600AST
Parameter Name Temp Level Min Typ Max Unit
ENCODE/CLK2×
Encode Rising to CLK2× Falling
3
t
CF
Full IV 6.5 8.0 9.5 ns
Encode Rising to CLK2× Rising
4
t
CR
Full IV t
CF
+ (t
ENCH
)/2 ns
@ Encode = 13 MSPS, 50% Duty Cycle Full IV 25.7 27.2 28.7 ns
@ Encode = 20 MSPS, 50% Duty Cycle Full IV 19.0 20.5 22.0 ns
CLK2×/DATA (D10:0, RSSI2:0)
5
CLK2× to DATA Rising Low Delay
3
t
2×_DRL
Full IV 3.0 6.5 ns
CLK2× to DATA Hold Time
3
t
H_D2×
Full IV 3.0 6.5 ns
CLK2× to DATA Falling Low
3, 6
t
2×_DFL
25°C IV 10.0 15.0 20.0 ns
Full IV 11.0 15.5 22.0 ns
CLK2× to DATA Setup Time
4
t
S_D2×
Full IV t
ENCH
– t
2×_DFL
ns
@ Encode = 13 MSPS, 50% Duty Cycle Full IV 16.5 23.0 ns
@ Encode = 20 MSPS, 50% Duty Cycle
6
25°C IV 5.0 10.0 ns
Full IV 3.0 9.5 ns
CLK2×/AB_OUT
5
CLK2× to AB_OUT Rising Low Delay
3
t
2×_ARL
Full IV 7.0 11.0 ns
CLK2× to AB_OUT Hold Time
3
t
H_A2×
Full IV 7.0 11.0 ns
CLK2× to AB_OUT Falling Low Delay
3, 6
t
2×_AFL
25°C IV 12.0 18.0 23.0 ns
Full IV 10.7 19.0 26.0 ns
CLK2× to AB_OUT Setup Time
4
t
S_A2×
Full IV t
ENCH
– t
2×_AFL
ns
@ Encode = 13 MSPS, 50% Duty Cycle Full IV 12.5 19.5 ns
@ Encode = 20 MSPS, 50% Duty Cycle
6
25°C IV 2.0 7.0 ns
Full IV –1.0 6.0 ns
ENCODE/DATA (D10:0, RSSI2:0)
ENCODE to DATA Rising Low Delay
4
t
EN_DRL
Full IV t
CR
+ t
2×_DRL
ns
ENCODE to DATA Hold Time
4
t
H_DEN
Full IV t
EN_DRL
ns
@ Encode = 13 MSPS, 50% Duty Cycle Full IV 28.7 33.7 ns
@ Encode = 20 MSPS, 50% Duty Cycle Full IV 22.0 27.0 ns
ENCODE to DATA Falling Low Delay
4
t
EN_DFL
Full IV t
CR
+ t
2×_DFL
ns
ENCODE to DATA Delay (Setup)
4
t
S_DEN
Full IV t
ENC
– t
EN_DFL
ns
@ Encode = 13 MSPS, 50% Duty Cycle Full IV 26.2 34.2 ns
@ Encode = 20 MSPS, 50% Duty Cycle
6
25°C IV 8.0 14.5 ns
Full IV 6.0 14.0 ns
ENCODE/AB_OUT
ENCODE to AB_OUT Rising Low Delay
4
t
EN_ARL
Full IV t
CR
+ t
2×_ARL
ns
ENCODE to AB_OUT Delay (Hold)
4
t
H_AEN
Full IV t
EN_ARL
ns
@ Encode = 13 MSPS, 50% Duty Cycle Full IV 32.7 38.2 ns
@ Encode = 20 MSPS, 50% Duty Cycle Full IV 26.0 31.5 ns
ENCODE to AB_OUT Falling Low Delay
4
t
EN_AFL
Full IV t
CR
+ t
2×_AFL
ns
ENCODE to AB_OUT Delay (Setup)
4
t
S_AEN
Full IV t
ENC
– t
EN_AFL
ns
@ Encode = 13 MSPS, 50% Duty Cycle Full IV 22.2 30.7 ns
@ Encode = 20 MSPS, 50% Duty Cycle
6
25°C IV 5.0 11.5 ns
Full IV 2.0 10.5 ns
NOTES
1
See AD6600 Timing Diagrams.
2
All switching specifications tested by driving ENC and ENC differentially.
3
This specification IS NOT a function of Encode period and duty cycle.
4
This specification IS a function of Encode period and duty cycle.
5
CLK2× referenced to 2.0 V crossing; digital output levels referenced to 0.8 V and 2.0 V crossings; all outputs with 10 pF load.
6
For these particular specifications, the 25°C specification is valid from 25°C to 85°C. The Full temperature specification includes cold temperature extreme and
covers the entire range, –40°C to +85°C.
Specifications subject to change without notice.
