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ATF750LVC-15XU

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
Features
• 3.0V to 5.5V Operating Range
• Advanced, High-speed, Electrically-erasable Programmable Logic Device
– Superset of 22V10
– Enhanced Logic Flexibility
– Architecturally Compatible with ATV750B and ATV750 Software and Hardware
• D- or T-type Flip-flop
• Product Term or Direct Input Pin Clocking
• 10 ns Maximum Pin-to-pin Delay with 5V Operation
• 15 ns Maximum Pin-to-pin Delay with 3V Operation
• Highest Density Programmable Logic Available in 24-pin Package
– Advanced Electrically-erasable Technology
– Reprogrammable
– 100% Tested
• Increased Logic Flexibility
– 42 Array Inputs, 20 Sum Terms and 20 Flip-flops
• Enhanced Output Logic Flexibility
– All 20 Flip-flops Feed Back Internally
– 10 Flip-flops are also Available as Outputs
• Programmable Pin-keeper Circuits
• Dual-in-line and Surface Mount Package in Standard Pinouts
• Commercial and Industrial Temperature Ranges
• 20-year Data Retention
• 2000V ESD Protection
• 1000 Erase/Write Cycles
• Green Package Options (Pb/Halide-free/RoHS Compliant) Available
1. Block Diagram
2. Description
The Atmel
®
“750” architecture is twice as powerful as most other 24-pin programma-
ble logic devices. Increased product terms, sum terms, flip-flops and output logic
configurations translate into more usable gates. High-speed logic and uniform, pre-
dictable delays guarantee fast in-system performance. The ATF750LVC is a high-
performance CMOS (electrically-erasable) complex programmable logic device
(CPLD) that utilizes Atmel’s proven electrically-erasable technology.
PROGRAMMABLE
INTERCONNECT
AND
COMBINATORIAL
LOGIC ARRAY
LOGIC
OPTION
(UP T0 20
FLIP-FLOPS)
OUTPUT
OPTION
4TO8
PRODUCT
TERMS
(OE PRODUCT TERMS)
10
I/O
PINS
12
INPUT
PINS
(CLOCK PIN)
High-speed
Complex
Programmable
Logic Device
ATF750LVC
1447F–PLD–11/08
2
1447F–PLD–11/08
ATF750LVC
3. Pin Configurations
Each of the ATF750LVC’s 22 logic pins can be used as an input. Ten of these can be used as
inputs, outputs or bi-directional I/O pins. Each flip-flop is individually configurable as either
D- or T-type. Each flip-flop output is fed back into the array independently. This allows burying
of all the sum terms and flip-flops.
There are 171 total product terms available. There are two sum terms per output, providing
added flexibility. A variable format is used to assign between four to eight product terms per
sum term. Much more logic can be replaced by this device than by any other 24-pin PLD. With
20 sum terms and flip-flops, complex state machines are easily implemented with logic to
spare.
Product terms provide individual clocks and asynchronous resets for each flip-flop. Each flip-
flop may also be individually configured to have direct input pin controlled clocking. Each out-
put has its own enable product term. One product term provides a common synchronous
preset for all flip-flops. Register preload functions are provided to simplify testing. All registers
automatically reset upon power-up.
Pin Name Function
CLK Clock
IN Logic Inputs
I/O Bi-directional Buffers
GND Ground
VCC 3V to 5.5V Supply
3.1 PLCC
Note: 1. For PLCC, pins 1, 8, 15, and 22 can
be left unconnected. For superior
performance, connect VCC to pin 1
and GND to pins 8, 15, and 22.
3.2 DIP/SOIC/TSSOP
5
6
7
8
9
10
11
25
24
23
22
21
20
19
IN
IN
IN
GND
(1)
IN
IN
IN
I/O
I/O
I/O
GND
(1)
I/O
I/O
I/O
4
3
2
1
28
27
26
12
13
14
15
16
17
18
IN
IN
GND
GND
(1)
IN
I/O
I/O
IN
IN
CLK/IN
VCC
(1)
VCC
I/O
I/O
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK/IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
3
1447F–PLD–11/08
ATF750LVC
6. Clock Mux
7. Output Options
4. Absolute Maximum Ratings*
Temperature Under Bias.................................. -40°C to +85°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Note: 1. Minimum voltage is -0.6V DC, which may under-
shoot to -2.0V for pulses of less than 20 ns.
Maximum output pin voltage is V
CC
+ 0.75V DC,
which may overshoot to 7V for pulses of less than
20 ns with VCC at VCC max.
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground ............................................-2.0V to +7V
(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V
(1)
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V
(1)
5. DC and AC Operating Conditions
Commercial Industrial
Operating Temperature (Ambient) 0°C - 70°C -40°C - +85°C
V
CC
Power Supply 3.0 - 5.25V 3.0 - 5.5V
SELECT
LOGIC
TO
CELL
CLOCK
PRODUCT
TERM
CLK
CKi
CKMUX
PIN
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

ATF750LVC-15XU

Mfr. #:
Buy ATF750LVC-15XU
Manufacturer:
Microchip Technology / Atmel
Description:
CPLD - Complex Programmable Logic Devices 750 GATE LOW POWER - 15NS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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