16
LTC1594/LTC1598
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APPLICATIONS INFORMATION
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edge, the S & H goes into hold mode and the conversion
begins. The voltage on the “COM” input must remain
constant and be free of noise and ripple throughout the
conversion time. Otherwise, the conversion operation
may not be performed accurately. The conversion time is
12 CLK cycles. Therefore, a change in the “COM” input
voltage during this interval can cause conversion errors.
For a sinusoidal voltage on the “COM” input this error
would be:
V
ERROR(MAX)
= V
PEAK
(2π)(f)(“COM”)12/f
CLK
Where f(“COM”) is the frequency of the “COM” input
voltage, V
PEAK
is its peak amplitude and f
CLK
is the
frequency of the CLK. In most cases V
ERROR
will not be
significant. For a 60Hz signal on the “COM” input to
generate a 1/4LSB error (305μV) with the converter
running at CLK = 320kHz, its peak value would have to be
8.425mV.
ANALOG INPUTS
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1594/
LTC1598 have capacitive switching input current spikes.
These current spikes settle quickly and do not cause a
problem. However, if large source resistances are used
or if slow settling op amps drive the inputs, care must be
taken to insure that the transients caused by the current
spikes settle completely before the conversion begins.
“Analog” Input Settling
The input capacitor of the LTC1594/LTC1598 is switched
onto the selected channel input during the t
SMPL
time (see
Figure 7) and samples the input signal within that time. The
sample phase is at least 1 1/2 CLK cycles before conver-
sion starts. The voltage on the “analog” input must settle
completely within t
SMPL
. Minimizing R
SOURCE
+
and C1 will
improve the input settling time. If a large “analog” input
source resistance must be used, the sample time can be
increased by using a slower CLK frequency.
“COM” Input Settling
At the end of the t
SMPL
, the input capacitor switches to the
“COM” input and conversion starts (see Figures 1 and 7).
During the conversion, the “analog” input voltage is
effectively “held” by the sample-and-hold and will not
affect the conversion result. However, it is critical that the
“COM” input voltage settles completely during the first
CLK cycle of the conversion time and be free of noise.
Minimizing R
SOURCE
and C2 will improve settling time.
If a large “COM” input source resistance must be used,
the time allowed for settling can be extended by using a
slower CLK frequency.
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settle within the allowed time
(see Figure 7). Again, the “analog” and “COM” input
sampling times can be extended as described above to
accommodate slower op amps. Most op amps, including
the LT
®
1006 and LT1413 single supply op amps, can be
made to settle well even with the minimum settling
windows of 4.8μs (“analog” input) which occur at the
maximum clock rate of 320kHz.
Source Resistance
The analog inputs of the LTC1594/LTC1598 look like a
20pF capacitor (C
IN
) in series with a 500Ω resistor (R
ON
)
and a 45Ω channel resistance as shown in Figure 8.
C
IN
gets switched between the selected “analog” and
“COM” inputs once during each conversion cycle. Large
external source resistors and capacitances will slow the
settling of the inputs. It is important that the overall RC
time constants be short enough to allow the analog
inputs to completely settle within the allowed time.
Figure 8. Analog Input Equivalent Circuit
R
ON
500Ω
R
ON
45Ω
C
IN
20pF
LTC1594
LTC1598
“ANALOG”
INPUT
R
SOURCE
+
V
IN
+
C1
“COM”
INPUT
MUXOUT
MUX
ADCIN
R
SOURCE
V
IN
C2
1594/98 • F08
17
LTC1594/LTC1598
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Input Leakage Current
Input leakage currents can also create errors if the source
resistance gets too large. For instance, the maximum
input leakage specification of 200nA (at 85°C) flowing
through a source resistance of 1.2k will cause a voltage
drop of 240μV or 0.2LSB. This error will be much
reduced at lower temperatures because leakage drops
rapidly (see typical curve Input Channel Leakage Current
vs Temperature).
REFERENCE INPUTS
The reference input of the LTC1594/LTC1598 is effec-
tively a 50k resistor from the time CS goes low to the end
of the conversion. The reference input becomes a high
impedance node at any other time (see Figure 9). Since
the voltage on the reference input defines the voltage
span of the A/D converter, the reference input should be
driven by a reference with low R
OUT
(ex. LT1004, LT1019
and LT1021) or a voltage source with low R
OUT
.
Reduced Reference Operation
The effective resolution of the LTC1594/LTC1598 can be
increased by reducing the input span of the converters.
The LTC1594/LTC1598 exhibit good linearity and gain
over a wide range of reference voltages (see typical
curves Change in Linearity vs Reference Voltage and
Change in Gain vs Reference Voltage). However, care
must be taken when operating at low values of V
REF
because of the reduced LSB step size and the resulting
higher accuracy requirement placed on the converters.
The following factors must be considered when operat-
ing at low V
REF
values:
1. Offset
2. Noise
3. Conversion speed (CLK frequency)
Offset with Reduced V
REF
The offset of the LTC1594/LTC1598 has a larger effect on
the output code when the ADCs are operated with
reduced reference voltage. The offset (which is typically
a fixed voltage) becomes a larger fraction of an LSB as the
size of the LSB is reduced. The typical curve of Change in
Offset vs Reference Voltage shows how offset in LSBs is
related to reference voltage for a typical value of V
OS
. For
example, a V
OS
of 122μV which is 0.1LSB with a 5V
reference becomes 0.5LSB with a 1V reference and
2.5LSBs with a 0.2V reference. If this offset is unaccept-
able, it can be corrected digitally by the receiving system
or by offsetting the “COM” input of the LTC1594/LTC1598.
Noise with Reduced V
REF
The total input referred noise of the LTC1594/LTC1598
can be reduced to approximately 400μV peak-to-peak
using a ground plane, good bypassing, good layout
techniques and minimizing noise on the reference inputs.
This noise is insignificant with a 5V reference but will
become a larger fraction of an LSB as the size of the LSB
is reduced.
For operation with a 5V reference, the 400μV noise is only
0.33LSB peak-to-peak. In this case, the LTC1594/LTC1598
noise will contribute virtually no uncertainty to the output
code. However, for reduced references the noise may
become a significant fraction of an LSB and cause
undesirable jitter in the output code. For example, with a
2.5V reference this same 400μV noise is 0.66LSB peak-
to-peak. This will reduce the range of input voltages over
which a stable output code can be achieved by 1LSB. If
the reference is further reduced to 1V, the 400μV noise
becomes equal to 1.65LSBs and a stable code may be
difficult to achieve. In this case averaging multiple read-
ings may be necessary.
This noise data was taken in a very clean setup. Any setup
induced noise (noise or ripple on V
CC
, V
REF
or V
IN
) will
add to the internal noise. The lower the reference voltage
to be used the more critical it becomes to have a clean,
noise free setup.
LTC1594
LTC1598
REF
+
R
OUT
V
REF
1
4
GND
1594/98 F09
Figure 9. Reference Input Equivalent Circuit
APPLICATIONS INFORMATION
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18
LTC1594/LTC1598
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Conversion Speed with Reduced V
REF
With reduced reference voltages, the LSB step size is
reduced and the LTC1594/LTC1598 internal comparator
overdrive is reduced. Therefore, it may be necessary to
reduce the maximum CLK frequency when low values of
V
REF
are used.
DYNAMIC PERFORMANCE
The LTC1594/LTC1598 have exceptional sampling capa-
bility. Fast Fourier Transform (FFT) test techniques are
used to characterize the ADC’s frequency response,
distortion and noise at the rated throughput. By applying
a low distortion sine wave and analyzing the digital
output using an FFT algorithm, the ADC’s spectral con-
tent can be examined for frequencies outside the funda-
mental. Figure 10 shows a typical LTC1594/LTC1598
plot.
APPLICATIONS INFORMATION
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Effective Number of Bits
The Effective Number of Bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to S/(N + D)
by the equation:
ENOB = [S/(N + D) – 1.76]/6.02
where S/(N + D) is expressed in dB. At the maximum
sampling rate of 16.8kHz with a 5V supply, the LTC1594/
LTC1598 maintain above 11 ENOBs at 10kHz input
frequency. Above 10kHz the ENOBs gradually decline, as
shown in Figure 11, due to increasing second harmonic
distortion. The noise floor remains low.
FREQUENCY (kHz)
0
–60
–40
0
35
1594/98 G14
–80
–100
12
467
–120
–140
–20
MAGNITUDE (dB)
T
A
= 25°C
V
CC
= V
REF
= 5V
f
IN
= 5kHz
f
CLK
= 320kHz
f
SMPL
= 12.5kHz
Figure 10. LTC1594/LTC1598 Nonaveraged, 4096 Point FFT Plot
INPUT FREQUENCY (kHz)
1
0
EFFECTIVE NUMBER OF BITS (ENOBs)
8
7
10
9
12
11
10 100 1000
1594/98 G10
6
50
44
62
56
74
68
38
5
4
3
2
1
T
A
= 25°C
V
CC
= 5V
f
CLK
= 320kHz
f
SMPL
= 16.8kHz
Figure 11. Effective Bits and S/(N + D) vs Input Frequency
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamen-
tal itself. The out-of-band harmonics alias into the fre-
quency band between DC and half of the sampling
frequency. THD is defined as:
THD =
++++
20log
VVV V
V
2
2
3
2
4
2
N
2
1
...
where V
1
is the RMS amplitude of the fundamental
frequency and V
2
through V
N
are the amplitudes of the
second through the N
th
harmonics. The typical THD
Signal-to-Noise Ratio
The Signal-to-Noise plus Distortion Ratio (S/N + D) is the
ratio between the RMS amplitude of the fundamental
input frequency to the RMS amplitude of all other fre-
quency components at the ADC’s output. The output is
band limited to frequencies above DC and below one half
the sampling frequency. Figure 11 shows a typical spec-
tral content with a 16.8kHz sampling rate.

LTC1598IG#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 8-Ch, uP Smpl 12-B Serial I/O A/D Conv
Lifecycle:
New from this manufacturer.
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