ADN2815ACPZ-RL7 Datasheet ADN2815ACPZ, ADN2815ACPZ-RL7, ADN2815ACPZ-500RL7 | P16-P18

Data Sheet ADN2815

Rev. C | Page 15 of 24

The CTRLB[7] bit defaults to 0. In this mode, the LOL pin

operates in the normal operating mode, that is, it is asserted

only when the ADN2815 is in acquisition mode and deasserts

when the ADN2815 has reacquired lock.

HARMONIC DETECTOR

The ADN2815 provides a harmonic detector, which detects

whether or not the input data has changed to a lower harmonic

of the data rate that the VCO is currently locked onto. For

example, if the input data instantaneously changes from OC-12,

622.08Mb/s to an OC-3, 155.52 Mb/s bit stream, this could be

perceived as a valid OC-12 bit stream, because the OC-3 data

pattern is exactly 4× slower than the OC-12 pattern. Therefore,

if the change in data rate is instantaneous, a 101 pattern at OC-3

would be perceived by the ADN2815 as a 111100001111 pattern

at OC-12. If the change to a lower harmonic is instantaneous, a

typical CDR could remain locked at the higher data rate.

The ADN2815 implements a harmonic detector that automati-

cally identifies whether or not the input data has switched to a

lower harmonic of the data rate that the VCO is currently

locked onto. When a harmonic is identified, the LOL pin is

asserted and a new frequency acquisition is initiated. The

ADN2815 automatically locks onto the new data rate, and the

LOL pin is deasserted.

However, the harmonic detector does not detect higher

harmonics of the data rate. If the input data rate switches to a

higher harmonic of the data rate, then the VCO is currently

locked onto, the VCO loses lock, the LOL pin is asserted, and a

new frequency acquisition is initiated. The ADN2815

automatically locks onto the new data rate.

The time to detect lock to harmonic is

× (T

/ρ)

where:

1/T

is the new data rate. For example, if the data rate is

switched from OC-12 to OC-3, then T

= 1/155.52 MHz.

ρ is the data transition density. Most coding schemes seek to

ensure that ρ = 0.5, for example, PRBS, 8B/10B.

When the ADN2815 is placed in lock to reference mode, the

harmonic detector is disabled.

SQUELCH MODE

Two SQUELCH modes are available with the ADN2815.

SQUELCH DATAOUT and CLKOUT mode is selected when

CTRLC[1] = 0 (default mode). In this mode, when the

SQUELCH input, Pin 27, is driven to a TTL high state, both the

clock and data outputs are set to the zero state to suppress

downstream processing. If the SQUELCH function is not

required, Pin 27 should be tied to VEE.

SQUELCH DATAOUT or CLKOUT mode is selected when

CTRLC[1] is 1. In this mode, when the SQUELCH input is

driven to a high state, the DATAOUTN/DATAOUTP pins are

squelched. When the SQUELCH input is driven to a low state,

the CLKOUT pins are squelched. This is especially useful in

repeater applications, where the recovered clock may not be

needed.

C INTERFACE

The ADN2815 supports a 2-wire, I

C compatible, serial bus

driving multiple peripherals. Two inputs, serial data (SDA) and

serial clock (SCK), carry information between any devices

connected to the bus. Each slave device is recognized by a

unique address. The ADN2815 has two possible 7-bit slave

addresses for both read and write operations. The MSB of the

7-bit slave address is factory programmed to 1. B5 of the slave

address is set by Pin 19, SADDR5. Slave Address Bits [4:0] are

defaulted to all 0s. The slave address consists of the 7 MSBs of

an 8-bit word. The LSB of the word either sets a read or write

operation (see Figure 6). Logic 1 corresponds to a read

operation, while Logic 0 corresponds to a write operation.

To control the device on the bus, the following protocol must be

followed. First, the master initiates a data transfer by establish-

ing a start condition, defined by a high-to-low transition on

SDA while SCK remains high. This indicates that an address/

data stream follows. All peripherals respond to the start

condition and shift the next eight bits (the 7-bit address and the

R/W bit). The bits are transferred from MSB to LSB. The

peripheral that recognizes the transmitted address responds by

pulling the data line low during the ninth clock pulse. This is

known as an acknowledge bit. All other devices withdraw from

the bus at this point and maintain an idle condition. The idle

condition is where the device monitors the SDA and SCK lines

waiting for the start condition and correct transmitted address.

The R/W bit determines the direction of the data. Logic 0 on the

LSB of the first byte means that the master writes information to

the peripheral. Logic 1 on the LSB of the first byte means that

the master reads information from the peripheral.

The ADN2815 acts as a standard slave device on the bus. The

data on the SDA pin is eight bits long, supporting the 7-bit

addresses, plus the R/W bit. The ADN2815 has eight subaddresses

to enable the user-accessible internal registers (see Table 6

through Table 10). It, therefore, interprets the first byte as the

device address and the second byte as the starting subaddress.

Autoincrement mode is supported, allowing data to be read

from or written to the starting subaddress and each subsequent

address without manually addressing the subsequent

subaddress. A data transfer is always terminated by a stop

condition. The user can also access any unique subaddress

ADN2815 Data Sheet

Rev. C | Page 16 of 24

Stop and start conditions can be detected at any stage of the

data transfer. If these conditions are asserted out of sequence

with normal read and write operations, they cause an

immediate jump to the idle condition. During a given SCK high

period, the user should issue one start condition, one stop

condition, or a single stop condition followed by a single start

condition. If an invalid subaddress is issued by the user, the

ADN2815 does not issue an acknowledge and returns to the idle

condition. If the user exceeds the highest subaddress while

reading back in autoincrement mode, then the highest subad-

dress register contents continue to be output until the master

device issues a no-acknowledge. This indicates the end of a

read. In a no-acknowledge condition, the SDATA line is not

pulled low on the ninth pulse. See Figure 7 and Figure 8 for

sample read and write data transfers and Figure 9 for a more

detailed timing diagram.

REFERENCE CLOCK (OPTIONAL)

A reference clock is not required to perform clock and data

recovery with the ADN2815. However, support for an optional

reference clock is provided. The reference clock can be driven

differentially or single-ended. If the reference clock is not being

used, then REFCLKP should be tied to VCC, and REFCLKN

can be left floating or tied to VEE (the inputs are internally

terminated to VCC/2). See Figure 16 through Figure 18 for

sample configurations.

The REFCLK input buffer accepts any differential signal with a

peak-to-peak differential amplitude of greater than 100 mV (for

example, LVPECL or LVDS) or a standard single-ended low

voltage TTL input, providing maximum system flexibility.

Phase noise and duty cycle of the reference clock are not critical

and 100 ppm accuracy is sufficient.

04952-0-021

100k

VCC/2

100k

ADN2815

REFCLKP

REFCLKN

BUFFER

Figure 16. Differential REFCLK Configuration

04952-0-022

100k

VCC/2

100k

ADN2815

REFCLKP

OUT

REFCLKN

BUFFER

VCC

CLK

OSC

Figure 17. Single-Ended REFCLK Configuration

04952-0-023

100k

VCC/2

100k

ADN2815

REFCLKP

REFCLKN

BUFFER

VCC

Figure 18. No REFCLK Configuration

The two uses of the reference clock are mutually exclusive. The

reference clock can be used either as an acquisition aid for the

ADN2815 to lock onto data or to measure the frequency of the

incoming data to within 0.01%. (There is the capability to

measure the data rate to approximately ±10% without the use of

a reference clock.) The modes are mutually exclusive because, in

the first use, the user knows exactly what the data rate is and

wants to force the part to lock onto only that data rate; in the

second use, the user does not know what the data rate is and

wants to measure it.

Lock-to-reference mode is enabled by writing a 1 to I

C Register

Bit CTRLA[0]. Fine data rate readback mode is enabled by

writing a 1 to I

C Register Bit CTRLA[1]. Writing a 1 to both of

these bits at the same time causes an indeterminate state and is

not supported.

Using the Reference Clock to Lock onto Data

In this mode, the ADN2815 locks onto a frequency derived

from the reference clock according to

Data Rate/2

CTRLA[5:2]

= REFCLK/2

CTRLA[7:6]

The user must know exactly what the data rate is and provide a

reference clock that is a function of this rate. The ADN2815 can

still be used as a continuous rate device in this configuration,

provided that the user has the ability to provide a reference

clock that has a variable frequency (see Application Note

AN-632).

The reference clock can be anywhere between 10 MHz and

160 MHz. By default, the ADN2815 expects a reference clock of

between 10 MHz and 20 MHz. If it is between 20 MHz and

40 MHz, 40 MHz and 80 MHz, or 80 MHz and 160 MHz, the

user needs to configure the ADN2815 to use the correct

reference frequency range by setting two bits of the CTRLA

Table 11. CTRLA Settings

CTRLA[7:6] Range (MHz) CTRLA[5:2] Ratio

00 10 to 20 0000 1

01 20 to 40 0001 2

10 40 to 80 n 2

11 80 to 160 1000 256

Data Sheet ADN2815

Rev. C | Page 17 of 24

The user can specify a fixed integer multiple of the reference

clock to lock onto using CTRLA[5:2], where CTRLA should be

set to the data rate/DIV_F

REF

, where DIV_F

REF

represents the

divided-down reference referred to the 10 MHz to 20 MHz

band. For example, if the reference clock frequency is

38.88 MHz and the input data rate is 622.08 Mb/s, then

CTRLA[7:6] is set to [01] to give a divided-down reference

clock of 19.44 MHz. CTRLA[5:2] is set to [0101], that is, 5,

because

622.08 Mb/s/19.44 MHz = 2

In this mode, if the ADN2815 loses lock for any reason, it

relocks onto the reference clock and continues to output a stable

clock.

While the ADN2815 is operating in lock-to-reference mode, if

the user ever changes the reference frequency, the F

REF

range

(CTRLA[7:6]) or the F

REF

ratio (CTRLA[5:2]), this must be

followed by writing a 0 to 1 transition into the CTRLA[0] bit to

initiate a new lock-to-reference command.

Using the Reference Clock to Measure Data Frequency

The user can also provide a reference clock to measure the

recovered data frequency. In this case, the user provides a

reference clock, and the ADN2815 compares the frequency of

the incoming data to the incoming reference clock and returns a

ratio of the two frequencies to 0.01% (100 ppm). The accuracy

error of the reference clock is added to the accuracy of the

ADN2815 data rate measurement. For example, if a 100 ppm

accuracy reference clock is used, the total accuracy of the

measurement is within 200 ppm.

The reference clock can range from 10 MHz and 160 MHz. The

ADN2815 expects a reference clock between 10 MHz and

20 MHz by default. If it is between 20 MHz and 40 MHz,

40 MHz and 80 MHz, or 80 MHz and 160 MHz, the user needs

to configure the ADN2815 to use the correct reference

frequency range by setting two bits of the CTRLA register,

CTRLA[7:6]. Using the reference clock to determine the

frequency of the incoming data does not affect the manner in

which the part locks onto data. In this mode, the reference clock

is used only to determine the frequency of the data. For this

reason, the user does not need to know the data rate to use the

reference clock in this manner.

Prior to reading back the data rate using the reference clock, the

CTRLA[7:6] bits must be set to the appropriate frequency range

with respect to the reference clock being used. A fine data rate

readback is then executed as follows:

1. Write a 1 to CTRLA[1]. This enables the fine data rate

measurement capability of the ADN2815. This bit is level

sensitive and does not need to be reset to perform subsequent

frequency measurements.

2. Reset MISC[2] by writing a 1 followed by a 0 to CTRLB[3].

This initiates a new data rate measurement.

3. Read back MISC[2]. If it is 0, the measurement is not

complete. If it is 1, the measurement is complete and the data

rate can be read back on FREQ[22:0]. The time for a data rate

measurement is typically 80 ms.

4. Read back the data rate from Registers FREQ2[6:0],

FREQ1[7:0], and FREQ0[7:0].

The data rate can be determined by

[ ]

( )

)_(

/..

RATESEL

REFCLK

DATARATE

fFREQf

×=

2022

where:

FREQ[22:0] is the reading from FREQ2[6:0] MSByte,

FREQ1[7:0], and FREQ0[7:0] LSByte.

DATAR ATE

is the data rate (Mb/s).

REFCLK

is the REFCLK frequency (MHz).

SEL_R AT E is the setting from CTRLA[7:6].

For example, if the reference clock frequency is 32 MHz,

SEL_RATE = 1, since the CTRLA[7:6] setting is [01], because

the reference frequency falls into the 20 MHz to 40 MHz range.

Assume for this example that the input data rate is 1.25 Gb/s

(GbE). After following Step 1 through Step 4, the value that is

read back on FREQ[22:0] = 0x138800, which is equal to 128 × 10

Plugging this value into the equation yields

128e6 × 32e6/2

(14+1)

= 1.25 Gb/s

If subsequent frequency measurements are required, CTRLA[1]

should remain set to 1. It does not need to be reset. The

measurement process is reset by writing a 1 followed by a 0 to

CTRLB[3]. This initiates a new data rate measurement. Follow

Step 2 through Step 4 to read back the new data rate.

Note that a data rate readback is valid only if LOL is low. If LOL

is high, the data rate readback is invalid.

Table 12.

D22 D21...D17 D16 D15 D14...D9 D8 D7 D6...D1 D0

FREQ2[6:0] FREQ1[7:0] FREQ0[7:0]

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

ADN2815ACPZ-RL7

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Analog Devices Inc.

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Timers & Support Products 12 Mbps - 1.3G ADN2812 Derivative IC.

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