Data Sheet ADN2815
Rev. C | Page 9 of 24
I
2
C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION
04952-0-007
1A500000X
MSB = 1 SET BY
PIN 19
0 = WR
1 = RD
SLAVE ADDRESS [6...0]
R/W
CTRL.
Figure 6. Slave Address Configuration
04952-0-008
S SLAVE ADDR, LSB = 0 (WR) A(S) A(S) A(S)DATASUB ADDR A(S) PDATA
Figure 7. I
2
C Write Data Transfer
04952-0-009
S
S = START BIT P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER
A(M) = LACK OF ACKNOWLEDGE BY MASTER
SSLAVE ADDR, LSB = 0 (WR) SLAVE ADDR, LSB = 1 (RD)A(S) A(S)SUB ADDR A(S) DATA A(M) DATA PA(M)
Figure 8. I
2
C Read Data Transfer
04952-0-010
START BIT
S
STOP BIT
P
ACKACKWR ACK
D0D7A0A7A5A6
SLADDR[4...0]
SLAVE ADDRESS SUB ADDRESS DATA
SUB ADDR[6...1] DATA[6...1]
SCK
SDA
Figure 9. I
2
C Data Transfer Timing
04952-0-011
t
BUF
SDA
SSPS
SCK
t
F
t
LOW
t
R
t
F
t
HD;STA
t
HD;DAT
t
SU;DAT
t
HIGH
t
SU;STA
t
SU;STO
t
HD;STA
t
R
Figure 10. I
2
C Port Timing Diagram
ADN2815 Data Sheet
Rev. C | Page 10 of 24
Table 6. Internal Register Map
1
Reg Name R/W Address D7 D6 D5 D4 D3 D2 D1 D0
FREQ0 R 0x0 MSB LSB
FREQ1
R
0x1
MSB
LSB
FREQ2 R 0x2 0 MSB LSB
RATE R 0x3 COARSE_RD[8] MSB Coarse Data Rate Readback COARSE_RD[1]
MISC R 0x4 x x x Static
LOL
LOL
Status
Data Rate
Measure
Complete
x COARSE_RD[0] LSB
CTRLA W 0x8 F
REF
Range Data Rate/DIV_F
REF
Ratio Measure Data Rate Lock to Reference
CTRLB W 0x9 Config
LOL
Reset
MISC[4]
System
Reset
0 Reset
MISC[2]
0 0 0
CTRLC W 0x11 0 0 0 0 0 0 SQUELCH Mode Output Boost
1
All writeable registers default to 0x00.
Table 7. Miscellaneous Register, MISC
Static LOL
LOL Status
Data Rate Measurement Complete
Coarse Rate Readback LSB
D7 D6 D5 D4 D3 D2 D1 D0
x x x 0 = Waiting for next LOL 0 = Locked 0 = Measuring data rate x COARSE_RD[0]
1 = Static LOL until reset 1 = Acquiring 1 = Measurement complete
Table 8. Control Register, CTRLA
1
F
REF
Range Data Rate/Div_F
REF
Ratio Measure Data Rate Lock to Reference
D7 D6 D5 D4 D3 D2 D1 D0
0
0
10 MHz to 20 MHz
0
0
0
0
1
Set to 1 to measure data rate
0 = Lock to input data
0 1 20 MHz to 40 MHz 0 0 0 1 2 1 = Lock to reference clock
1 0 40 MHz to 80 MHz 0 0 1 0 4
1 1 80 MHz to 160 MHz n 2
n
1 0 0 0 256
1
Where DIV_F
REF
is the divided down reference referred to the 10 MHz to 20 MHz band (see the Reference Clock (Optional) section).
Table 9. Control Register, CTRLB
Config LOL Reset MISC[4] System Reset Reset MISC[2]
D7 D6 D5 D4 D3 D2 D1 D0
0 = LOL pin normal operation Write a 1 followed by
0 to reset MISC[4]
Write a 1 followed by
0 to reset ADN2815
Set to 0 Write a 1 followed by
0 to reset MISC[2]
Set to 0 Set to 0 Set to 0
1 = LOL pin is static LOL
Table 10. Control Register, CTRLC
SQUELCH Mode Output Boost
D7 D6 D5 D4 D3 D2 D1 D0
Set to 0 Set to 0 Set to 0 Set to 0 Set to 0 Set to 0 0 = SQUELCH CLK and DATA 0 = Default output swing
1 = SQUELCH CLK or DATA 1 = Boost output swing
Data Sheet ADN2815
Rev. C | Page 11 of 24
JITTER SPECIFICATIONS
The ADN2815 CDR is designed to achieve the best bit-error-
rate (BER) performance and exceeds the jitter transfer, genera-
tion, and tolerance specifications proposed for SONET/SDH
equipment defined in the Telcordia Technologies specification.
Jitter is the dynamic displacement of digital signal edges from
their long-term average positions, measured in unit intervals
(UI), where 1 UI = 1 bit period. Jitter on the input data can
cause dynamic phase errors on the recovered clock sampling
edge. Jitter on the recovered clock causes jitter on the
retimed data.
The following sections briefly summarize the specifications of
jitter generation, transfer, and tolerance in accordance with the
Telcordia document (GR-253-CORE, Issue 3, September 2000)
for the optical interface at the equipment level and the
ADN2815 performance with respect to those specifications.
Jitter Generation
The jitter generation specification limits the amount of jitter
that can be generated by the device with no jitter and wander
applied at the input. For SONET devices, the jitter generated
must be less than 0.01 UI rms, and must be less than 0.1 UI p-p.
Jitter Transfer
The jitter transfer function is the ratio of the jitter on the output
signal to the jitter applied on the input signal vs. the frequency.
This parameter measures the limited amount of the jitter on an
input signal that can be transferred to the output signal (see
Figure 11).
04952-0-015
0.1
ACCEPTABLE
RANGE
f
C
JITTER FREQUENCY (kHz)
SLOPE = –20dB/DECADE
JITTER GAIN (dB)
Figure 11. Jitter Transfer Curve
Jitter Tolerance
The jitter tolerance is defined as the peak-to-peak amplitude of
the sinusoidal jitter applied on the input signal, which causes a
1 dB power penalty. This is a stress test intended to ensure that
no additional penalty is incurred under the operating
conditions (see Figure 12).
04952-0-016
15.00
1.50
0.15
f
0
f
1
f
2
f
3
f
4
JITTER FREQUENCY (kHz)
SLOPE = –20dB/DECADE
INPUT JITTER AMPLITUDE (UI p-p)
Figure 12. SONET Jitter Tolerance Mask

ADN2815ACPZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Timers & Support Products Anyrate 10 Mbps to 2.7Gbps PA/CDR
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet