ADN2815ACPZ Datasheet ADN2815ACPZ, ADN2815ACPZ-RL7, ADN2815ACPZ-500RL7 | P13-P15

ADN2815 Data Sheet

Rev. C | Page 12 of 24

THEORY OF OPERATION

The ADN2815 is a delay- and phase-locked loop circuit for

clock recovery and data retiming from an NRZ encoded data

stream. The phase of the input data signal is tracked by two

separate feedback loops that share a common control voltage. A

high speed delay-locked loop path uses a voltage controlled

phase shifter to track the high frequency components of input

jitter. A separate phase control loop, comprised of the VCO,

tracks the low frequency components of input jitter. The initial

frequency of the VCO is set by yet a third loop, which compares

the VCO frequency with the input data frequency and sets the

coarse tuning voltage. The jitter tracking phase-locked loop

(PLL) controls the VCO by the fine-tuning control.

The delay and phase loops together track the phase of the input

data signal. For example, when the clock lags input data, the

phase detector drives the VCO to a higher frequency and

increases the delay through the phase shifter; both of these

actions serve to reduce the phase error between the clock and

data. The faster clock picks up phase, while the delayed data

loses phase. Because the loop filter is an integrator, the static

phase error is driven to zero.

Another view of the circuit is that the phase shifter implements

the zero required for frequency compensation of a second-order

phase-locked loop, and this zero is placed in the feedback path

and, thus, does not appear in the closed-loop transfer function.

Jitter peaking in a conventional second-order phase-locked loop

is caused by the presence of this zero in the closed-loop transfer

function. Because this circuit has no zero in the closed-loop

transfer, jitter peaking is minimized.

The delay and phase loops together simultaneously provide

wideband jitter accommodation and narrow-band jitter

filtering. The linearized block diagram in Figure 13 shows that

the jitter transfer function, Z(s)/X(s), is a second-order low-pass

providing excellent filtering. Note that the jitter transfer has no

zero, unlike an ordinary second-order phase-locked loop. This

means that the main PLL has virtually zero jitter peaking (see

Figure 14). This makes this circuit ideal for signal regenerator

applications where jitter peaking in a cascade of regenerators

can contribute to hazardous jitter accumulation.

The error transfer, e(s)/X(s), has the same high-pass form as an

ordinary phase-locked loop. This transfer function is free to be

optimized to give excellent wideband jitter accommodation,

because the jitter transfer function, Z(s)/X(s), provides the

narrow-band jitter filtering.

04952-0-017

X(s)

Z(s)

RECOVERED

CLOCK

e(s)

INPU

DATA

d/sc

psh

o/s

1/n

d = PHASE DETECTOR GAI

o = VCO GAIN

c = LOOP INTEGRATO

psh = PHASE SHIFTER GAI

n = DIVIDE RATI

n psh

s+ 1

Z(s)

X(s)

JITTER TRANSFER FUNCTION

d psh

s++

e(s)

X(s)

TRACKING ERROR TRANSFER FUNCTION

Figure 13. ADN2815 PLL/DLL Architecture

ADN2815

Z(s)

X(s)

04952-0-018

FREQUENCY (kHz)

JITTER PEAKING

IN ORDINARY PLL

JITTER GAIN (dB)

n psh

d psh

Figure 14. ADN2815 Jitter Response vs. Conventional PLL

The delay and phase loops contribute to overall jitter accom-

modation. At low frequencies of input jitter on the data signal,

the integrator in the loop filter provides high gain to track large

jitter amplitudes with small phase error. In this case, the VCO is

frequency modulated and jitter is tracked as in an ordinary

phase-locked loop. The amount of low frequency jitter that can

be tracked is a function of the VCO tuning range. A wider

tuning range gives larger accommodation of low frequency

jitter. The internal loop control voltage remains small for small

phase errors; therefore, the phase shifter remains close to the

center of its range and thus contributes little to the low

frequency jitter accommodation.

Data Sheet ADN2815

Rev. C | Page 13 of 24

At medium jitter frequencies, the gain and tuning range of the

VCO are not large enough to track input jitter. In this case, the

VCO control voltage becomes large and saturates, and the VCO

frequency dwells at one extreme of its tuning range or at the

other. The size of the VCO tuning range, therefore, has only a

small effect on the jitter accommodation. The delay-locked loop

control voltage is now larger, and therefore the phase shifter

takes on the burden of tracking the input jitter. The phase

shifter range, in UI, can be seen as a broad plateau on the jitter

tolerance curve. The phase shifter has a minimum range of 2 UI

at all data rates.

The gain of the loop integrator is small for high jitter

frequencies; therefore, larger phase differences are needed to

make the loop control voltage large enough to tune the range of

the phase shifter. Large phase errors at high jitter frequencies

cannot be tolerated. In this region, the gain of the integrator

determines the jitter accommodation. Because the gain of the

loop integrator declines linearly with frequency, jitter accom-

modation is lower with higher jitter frequency. At the highest

frequencies, the loop gain is very small, and little tuning of the

phase shifter can be expected. In this case, jitter accommodation is

determined by the eye opening of the input data, the static

phase error, and the residual loop jitter generation. The jitter

accommodation is roughly 0.5 UI in this region. The corner

frequency between the declining slope and the flat region is

the closed loop bandwidth of the delay-locked loop, which is

roughly 1.5 MHz at 1.25 Gb/s.

ADN2815 Data Sheet

Rev. C | Page 14 of 24

FUNCTIONAL DESCRIPTION

FREQUENCY ACQUISITION

The ADN2815 acquires frequency from the data over a range of

data frequencies from 10 Mb/s to 1.25 Gb/s. The lock detector

circuit compares the frequency of the VCO and the frequency

of the incoming data. When these frequencies differ by more

than 1000 ppm, LOL is asserted. This initiates a frequency

acquisition cycle. The VCO frequency is reset to the bottom of

its range, which is 10 MHz. The frequency detector then

compares this VCO frequency and the incoming data frequency

and increments the VCO frequency, if necessary. Initially, the

VCO frequency is incremented in large steps to aid fast acquisi-

tion. As the VCO frequency approaches the data frequency, the

step size is reduced until the VCO frequency is within 250 ppm

of the data frequency, at which point LOL is deasserted.

Once LOL is deasserted, the frequency-locked loop is turned

off. The PLL/DLL pulls in the VCO frequency the rest of the

way until the VCO frequency equals the data frequency.

The frequency loop requires a single external capacitor between

CF1 and CF2, Pin 14 and Pin 15. A 0.47 µF ± 20%, X7R ceramic

chip capacitor with < 10 nA leakage current is recommended.

Leakage current of the capacitor can be calculated by dividing

the maximum voltage across the 0.47 µF capacitor, ~3 V, by the

insulation resistance of the capacitor. The insulation resistance

of the 0.47 µF capacitor should be greater than 300 MΩ.

INPUT BUFFER

The input buffer has differential inputs (PIN/NIN), which are

internally terminated with 50 Ω to an on-chip voltage reference

(VREF = 2.5 V typically). The minimum differential input level

required to achieve a BER of 10

−10

is 200 mV p-p.

LOCK DETECTOR OPERATION

The lock detector on the ADN2815 has three modes of

operation: normal mode, REFCLK mode, and static LOL mode.

Normal Mode

In normal mode, the ADN2815 is a continuous rate CDR that

locks onto any data rate from 10 Mb/s to 1.25 Gb/s without the

use of a reference clock as an acquisition aid. In this mode, the

lock detector monitors the frequency difference between the

VCO and the input data frequency, and deasserts the loss-of-

lock signal, which appears on Pin 16 (LOL), when the VCO is

within 250 ppm of the data frequency. This enables the D/PLL,

which pulls the VCO frequency in the remaining amount and

acquires phase lock. Once locked, if the input frequency error

exceeds 1000 ppm (0.1%), the loss-of-lock signal is reasserted

and control returns to the frequency loop, which begins a new

frequency acquisition starting at the lowest point in the VCO

operating range, 10 MHz. The LOL pin remains asserted until

the VCO locks onto a valid input data stream to within

250 ppm frequency error. This hysteresis is shown in Figure 15.

04952-0-020

LOL

0–

250 250 1000 f

VCO

ERROR

(ppm)

–

1000

Figure 15. Transfer Function of LOL

LOL Detector Operation Using a Reference Clock

In REFCLK mode, a reference clock is used as an acquisition aid

to lock the ADN2815 VCO. Lock-to-reference mode is enabled

by setting CTRLA[0] to 1. The user also needs to write to the

CTRLA[7:6] and CTRLA[5:2] bits to set the reference

frequency range and the divide ratio of the data rate with

respect to the reference frequency. For more details, see the

Reference Clock (Optional) section. In this mode, the lock

detector monitors the difference in frequency between the

divided down VCO and the divided down reference clock. The

loss-of-lock signal, which appears on Pin 16 (LOL), is

deasserted when the VCO is within 250 ppm of the desired

frequency. This enables the D/PLL, which pulls the VCO

frequency in the remaining amount with respect to the input

data and acquires phase lock. Once locked, if the input

frequency error exceeds 1000 ppm (0.1%), the loss-of-lock

signal is reasserted and control returns to the frequency loop,

which reacquires with respect to the reference clock. The LOL

pin remains asserted until the VCO frequency is within

250 ppm of the desired frequency. This hysteresis is shown in

Figure 15.

Static LOL Mode

The ADN2815 implements a static LOL feature, which indicates

if a loss-of-lock condition has ever occurred and remains

asserted, even if the ADN2815 regains lock, until the static LOL

bit is manually reset. The I

C register bit, MISC[4], is the static

LOL bit. If there is ever an occurrence of a loss-of-lock

condition, this bit is internally asserted to logic high. The

MISC[4] bit remains high even after the ADN2815 has

reacquired lock to a new data rate. This bit can be reset by

writing a 1 followed by 0 to I

C Register Bit CTRLB[6]. Once

reset, the MISC[4] bit remains deasserted until another loss-of-

lock condition occurs.

Writing a 1 to I

C Register Bit CTRLB[7] causes the LOL pin,

Pin 16, to become a static LOL indicator. In this mode, the LOL

pin mirrors the contents of the MISC[4] bit and has the

functionality described in the previous paragraph.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

ADN2815ACPZ

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Manufacturer:

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Timers & Support Products Anyrate 10 Mbps to 2.7Gbps PA/CDR

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ADN2815ACPZ

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