74ABT899CMSAX Datasheet 74ABT899CSC, 74ABT899CMSA, 74ABT899CMSAX | P1-P3

November 1992

Revised January 1999

74ABT899 9-Bit Latchable Transceiver with Parity Generator/Checker

74ABT899

9-Bit Latchable Transceiver

with Parity Generator/Checker

General Description

The ABT899 is a 9-bit to 9-bit parity transceiver with trans-

parent latches. The device can operate as a feed-through

transceiver or it can generate/check parity from the 8-bit

data busses in either direction.

The ABT899 features independent latch enables for the A-

to-B direction and the B-to-A direction, a select pin for

ODD/EVEN

parity, and separate error signal output pins for

checking parity.

Features

■ Latchable transceiver with output sink of 64 mA

■ Option to select generate parity and check or

“feed-through” data/parity in directions A-to-B or B-to-A

■ Independent latch enables for A-to-B and B-to-A

directions

■ Select pin for ODD/EVEN

parity

■ ERRA

and ERRB output pins for parity checking

■ Ability to simultaneously generate and check parity

■ May be used in systems applications in place of the

543 and 280

■ May be used in system applications in place of the

657 and 373 (no need to change T/R

to check parity)

■ Guaranteed output skew

■ Guaranteed multiple output switching specifications

■ Output switching specified for both 50 pF and

250 pF loads

■ Guaranteed simultaneous switching noise level and

dynamic threshold performance

■ Guaranteed latchup protection

■ High impedance glitch free bus loading during entire

power up and power down cycle

■ Nondestructive hot insertion capability

■ Disable time less than enable time to avoid bus

contention

Ordering Code:

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagrams

Pin Assignment

for PLCC

Pin Assignment for

SOIC and SSOP

Order Number Package Number Package Description

74ABT899CSC M28B 28-Lead Small Outline Integrated Circuit (SOIC), MS-013, 0.300” Wide Body

74ABT899CMSA MSA28 28-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide

74ABT899CQC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450” Square

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74ABT899

Pin Descriptions Functional Description

The ABT899 has three principal modes of operation which

are outlined below. These modes apply to both the A-to-B

and B-to-A directions.

• Bus A (B) communicates to Bus B (A), parity is gener-

ated and passed on to the B (A) Bus as BPAR (APAR). If

LEB (LEA) is HIGH and the Mode Select (SEL

) is LOW,

the parity generated from B[0:7] (A[0:7]) can be checked

and monitored by ERRB

(ERRA).

• Bus A (B) communicates to Bus B (A) in a feed-through

mode if SEL

is HIGH. Parity is still generated and

checked as ERRA

and ERRB in the feed-through mode

(can be used as an interrupt to signal a data/parity bit

error to the CPU).

• Independent Latch Enables (LEA and LEB) allow other

permutations of generating/checking (see Function

Table below).

Function Table

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Note 1: O/E

= ODD/EVEN

Pin Names Descriptions

–A

A Bus Data Inputs/Data Outputs

–B

B Bus Data Inputs/Data Outputs

APAR, BPAR A and B Bus Parity Inputs/Outputs

ODD/EVEN

ODD/EVEN Parity Select,

Active LOW for EVEN Parity

GBA

, GAB Output Enables for A or B Bus,

Active LOW

SEL

Select Pin for Feed-Through or

Generate Mode, LOW for Generate

Mode

LEA, LEB Latch Enables for A and B Latches,

HIGH for Transparent Mode

ERRA

, ERRB Error Signals for Checking Generated

Parity with Parity In, LOW if Error

Occurs

Inputs Operation

GAB

GBA SEL LEA LEB

H H X X X Busses A and B are 3-STATE.

H L L L H Generates parity from B[0:7] based on O/E

(Note 1). Generated parity → APAR.

Generated parity checked against BPAR and output as ERRB

HLLHH

Generates parity from B[0:7] based on O/E

. Generated parity → APAR. Gener-

ated parity checked against BPAR and output as ERRB

. Generated parity also

fed back through the A latch for generate/check as ERRA

HLLXL

Generates parity from B latch data based on O/E

. Generated parity → APAR.

Generated parity checked against latched BPAR and output as ERRB

H L H X H BPAR/B[0:7] → APAR/A0:7] Feed-through mode. Generated parity checked

against BPAR and output as ERRB

H L H H H BPAR/B[0:7] → APAR/A[0:7]

Feed-through mode. Generated parity checked against BPAR and output as

ERRB

. Generated parity also fed back through the A latch for generate/check as

ERRA

LHLHL

Generates parity for A[0:7] based on O/E

. Generated parity → BPAR. Gener-

ated parity checked against APAR and output as ERRA

LHLHH

Generates parity from A[0:7] based on O/E

. Generated parity → BPAR. Gener-

ated parity checked against APAR and output as ERRA

. Generated parity also

fed back through the B latch for generate/check as ERRB

LHLLX

Generates parity from A latch data based on O/E

. Generated parity → BPAR.

Generated parity checked against latched APAR and output as ERRA

L H H H L APAR/A[0:7] → BPAR/B[0:7]

Feed-through mode. Generated parity checked against APAR and output as

ERRA

L H H H H APAR/A[0:7] → BPAR/B[0:7]

Feed-through mode. Generated parity checked against APAR and output as

ERRA

. Generated parity also fed back through the B latch for generate/check as

ERRB

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74ABT899

Functional Block Diagram

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

74ABT899CMSAX

Mfr. #:

Buy 74ABT899CMSAX

Manufacturer:

ON Semiconductor

Description:

TXRX W/GENERATOR&CHECKER 28SSOP

Lifecycle:

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74ABT899CMSAX

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