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74ABT899CMSAX

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
7 www.fairchildsemi.com
74ABT899
Extended AC Electrical Characteristics
(SOIC and PLCC Package)
Note 9: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-
HIGH, HIGH-to-LOW, etc.).
Note 10: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac-
itors in the standard AC load. This specification pertains to single output switching only.
Note 11: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-
HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load
Note 12: The 3-STATE delay time is dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet.
Note 13: Not applicable for multiple output switching.
Symbol Parameter
T
A
= +25°CT
A
= −40°C to +85°CT
A
= −40°C to +85°C
Units
V
CC
= +5.0V V
CC
= 4.5V–5.5V V
CC
= 4.5V–5.5V
C
L
= 50 pF C
L
= 250 pF C
L
= 250 pF
9 Outputs Switching 1 Output Switching 9 Outputs Switching
(Note 9) (Note 10) (Note 11)
Min Typ Max Min Max Min Max
f
TOGGLE
Max Toggle Frequency 100 MHz
t
PLH
Propagation Delay 1.5 6.2 2.0 7.2 2.5 9.5
ns
t
PHL
A
n
to B
n
1.5 6.2 2.0 7.2 2.5 9.5
t
PLH
Propagation Delay 1.5 6.8 2.0 8.0 2.5 10.0 ns
t
PHL
APAR to BPAR 1.5 6.8 2.0 8.0 2.0 10.0
t
PLH
Propagation Delay 2.5 10.0 3.0 12.5 3.5 13.5 ns
t
PHL
A
n
, B
n
to BPAR, APAR 2.5 10.0 3.0 12.5 3.5 13.5
t
PLH
Propagation Delay (Note 13) 3.0 12.0 (Note 13) ns
t
PHL
A
n
, B
n
to ERRA, ERRB
3.0 12.0
t
PLH
Propagation Delay (Note 13) 2.0 9.0 (Note 13) ns
t
PHL
APAR, BPAR to ERRA, ERRB
2.0 9.0
t
PLH
Propagation Delay (Note 13) 2.5 9.9 (Note 13) ns
t
PHL
ODD/EVEN to APAR, BPAR 2.5 9.9
t
PLH
Propagation Delay (Note 13) 2.0 8.8 (Note 13) ns
t
PHL
ODD/EVEN to ERRA, ERRB
2.0 8.8
t
PLH
Propagation Delay (Note 13) 2.0 9.5 (Note 13) ns
t
PHL
SEL to APAR, BPAR 2.0 9.5
t
PLH
Propagation Delay 1.5 5.7 2.0 7.9 2.5 10.0 ns
t
PHL
LEA, LEB to B
n
, A
n
1.5 5.7 2.0 7.9 2.5 10.0
t
PLH
Propagation Delay 1.5 9.5 2.0 12.0 2.5 13.0 ns
t
PHL
LEA, LEB to BPAR, APAR 1.5 9.5 2.0 12.0 2.5 13.0
t
PLH
Propagation Delay (Note 13) 2.0 11.5 (Note 13) ns
t
PHL
LEA, LEB to ERRA, ERRB
2.0 11.5
t
PZH
Output enable time 1.5 7.0 2.0 8.5 2.5 10.5
t
PZL
GBA or GAB to A
n
,
1.5 7.0 2.0 8.5 2.5 10.5 ns
APAR or B
n
, BPAR
t
PHZ
Output disable time 1.0 6.5
t
PLZ
GBA or GAB to A
n
,
1.0 6.5 (Note 12) (Note 12) ns
APAR or B
n
, BPAR
www.fairchildsemi.com 8
74ABT899
Extended AC Electrical Characteristics
(SSOP Package)
Note 14: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-
HIGH, HIGH-to-LOW, etc.).
Note 15: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac-
itors in the standard AC load. This specification pertains to single output switching only.
Note 16: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-
HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load
Note 17: The 3-STATE delay time is dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet.
Note 18: Not applicable for multiple output switching.
Symbol Parameter
T
A
= +25°CT
A
= −40°C to +85°CT
A
= −40°C to +85°C
Units
V
CC
= +5.0V V
CC
= 4.5V–5.5V V
CC
= 4.5V–5.5V
C
L
= 50 pF C
L
= 250 pF C
L
= 250 pF
9 Outputs Switching 1 Output Switching 9 Outputs Switching
(Note 14) (Note 15) (Note 16)
Min Typ Max Min Max Min Max
f
TOGGLE
Max Toggle Frequency 100 MHz
t
PLH
Propagation Delay 1.5 6.7 2.0 7.7 2.5 10.1
ns
t
PHL
A
n
to B
n
1.5 6.7 2.0 7.7 2.5 10.1
t
PLH
Propagation Delay 1.5 7.3 2.0 8.5 2.5 10.6 ns
t
PHL
APAR to BPAR 1.5 7.3 2.0 8.5 2.0 10.6
t
PLH
Propagation Delay 2.5 10.7 3.0 13.2 3.5 14.3 ns
t
PHL
A
n
, B
n
to BPAR, APAR 2.5 10.7 3.0 13.2 3.5 14.3
t
PLH
Propagation Delay (Note 18) 3.0 12.9 (Note 18) ns
t
PHL
A
n
, B
n
to ERRA, ERRB
3.0 12.9
t
PLH
Propagation Delay (Note 18) 2.0 9.5 (Note 18) ns
t
PHL
APAR, BPAR to ERRA, ERRB
2.0 9.5
t
PLH
Propagation Delay (Note 18) 2.5 10.4 (Note 18) ns
t
PHL
ODD/EVEN to APAR, BPAR 2.5 10.4
t
PLH
Propagation Delay (Note 18) 2.0 9.3 (Note 18) ns
t
PHL
ODD/EVEN to ERRA, ERRB
2.0 9.3
t
PLH
Propagation Delay (Note 18) 2.0 10.0 (Note 18) ns
t
PHL
SEL to APAR, BPAR 2.0 10.0
t
PLH
Propagation Delay 1.5 6.2 2.0 8.4 2.5 10.6 ns
t
PHL
LEA, LEB to B
n
, A
n
1.5 6.2 2.0 8.4 2.5 10.6
t
PLH
Propagation Delay 1.5 10.0 2.0 12.5 2.5 13.6 ns
t
PHL
LEA, LEB to BPAR, APAR 1.5 10.0 2.0 12.5 2.5 13.6
t
PLH
Propagation Delay (Note 18) 2.0 12.0 (Note 18) ns
t
PHL
LEA, LEB to ERRA, ERRB
2.0 12.0
t
PZH
Output enable time 1.5 7.5 2.0 9.0 2.5 11.1
t
PZL
GBA or GAB to A
n
,
1.5 7.5 2.0 9.0 2.5 11.1 ns
APAR or B
n
, BPAR
t
PHZ
Output disable time 1.0 7.0
t
PLZ
GBA or GAB to A
n
,
1.0 7.0 (Note 17) (Note 17) ns
APAR or B
n
, BPAR
9 www.fairchildsemi.com
74ABT899
Skew
(PLCC package) (Note 2)
Note 19: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-
HIGH, HIGH-to-LOW, etc.).
Note 20: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 21: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH to LOW (t
OSHL
), LOW to HIGH (t
OSLH
), or any combination switching LOW to HIGH and/or HIGH to
LOW (t
OST
). This specification is guaranteed but not tested. Skew applies to propagation delays individually; i.e., A
n
to B
n
separate from LEA to A
n
.
Note 22: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Note 23: Propagation delay variation for a given set of conditions (i.e., temperature and V
CC
) from device to device. This specification is guaranteed but not
tested.
Capacitance
Note 24: C
I/O
is measured at frequency, f = 1 MHz, per MIL-STD-883B, Method 3012.
Symbol Parameter
T
A
= −40°C to +85°CT
A
= −40°C to +85°C
Units
V
CC
= 4.5V–5.5V V
CC
= 4.5V–5.5V
C
L
= 50 pF C
L
= 250 pF
9 Outputs Switching 9 Outputs Switching
(Note 19) (Note 20)
Max Max
t
OSHL
Pin to Pin Skew 1.0 2.0 ns
(Note 21) HL Transitions
t
OSLH
Pin to Pin Skew 1.1 2.1 ns
(Note 21) LH Transitions
t
PS
Duty Cycle 2.0 3.5 ns
(Note 22) LH–HL Skew
t
OST
Pin to Pin Skew 2.0 3.5 ns
(Note 21) LH/HL Transitions
t
PV
Device to Device Skew 3.0 4.0 ns
(Note 23) LH/HL Transitions
Symbol Parameter Typ Units
Conditions
T
A
= 25°C
C
IN
Input Pin Capacitance 5.0 pF V
CC
= 0V
C
I/O
(Note 24) Output Capacitance 11.0 pF V
CC
= 5.0V
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

74ABT899CMSAX

Mfr. #:
Buy 74ABT899CMSAX
Manufacturer:
ON Semiconductor
Description:
TXRX W/GENERATOR&CHECKER 28SSOP
Lifecycle:
New from this manufacturer.
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