© Semiconductor Components Industries, LLC, 2011
April, 2011 Rev. 1
1 Publication Order Number:
NCP4330/D
NCP4330
Post Regulation Driver
The NCP4330 houses a dual MOSFET driver intended to be used as
a companion chip in ACDC or DCDC multioutput post regulated
power supplies. Being directly fed by the secondary AC signal, the
device keeps power dissipation to the lowest while reducing the
surrounding part count. Furthermore, the implementation of a
Nchannel MOSFET gives NCP4330based applications a significant
advantage in terms of efficiency.
Features
Undervoltage Lockout
Thermal Shutdown for Overtemperature Protection
PWM Operation Synchronized to the Converter Frequency
High Gate Drive Capability
Bootstrap for NMOSFET HighSide Drive
OverLap Management for Soft Switching
High Efficiency PostRegulation
Ideal for Frequencies up to 400 kHz
This is a PbFree Device
Typical Applications
ATX 3V3 PostRegulation
Offline SMPS with MAGAMP PostRegulation
MultiOutputs DCDC Converters
Buffer
AR2
Buffer
AR3
Current
Mirror
2.5 V/1.5 V
Level
Shifter
BandGap
UVD
Vref, UVDth
Comparator
Iramp
BST
HS_DRV
LS_DRV
C_ramp
I_ramp
GND
RST
RESET Block
U1
INVERTER
Iramp
Hysteresis
HS_DRV and
-
+
LS_DRV low
Figure 1. Block Diagram
V
DD
V
DD
V
DD
V
DD
V
DD
Undervoltage Detection
(UVD high if V
DD
< 4.9 V)
U3
OR
U4
1
8
ORDERING INFORMATION
Device Package Shipping
NCP4330DR2G SO8
(PbFree)
2500 / Tape & Reel
1
HS_DRV
8
GND
2
BST
3
RST
4
C_ramp
7
LS_DRV
6
V
DD
5
I_ramp
(Top View)
MARKING
DIAGRAM
SO8
D SUFFIX
CASE 751
4330D = Device Number
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
PIN CONNECTIONS
http://onsemi.com
4330D
ALYW
G
1
8
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
NCP4330
http://onsemi.com
2
Figure 2. Timing Diagram(s)
Converter Winding
Voltage
C_ramp Voltage
HighSide Driver
LowSide Driver
100 ns delay
VrefH
Time
(referenced to
HS MOSFET source)
Time
Time
Time
0 V
0 V
VrefL
Time
Synchronization
Signal
Time
Internal RESET
Signal
100 ns delay
2.55 V
DETAILED PIN DESCRIPTION(S)
Pin
Number
Name Function
1 HS_DRV “HS_DRV” is the gate driver of the highside MOSFET.
2 BST
“BST” is the bootstrap pin. A 0.1 mF to 1.0 mF ceramic capacitor should be connected between this pin
and the node that is common to the coil and the two MOSFET. The “BST” voltage feeds the highside
driver (“HS_DRV”).
3 RST The “RST” pin resets the C_ramp voltage in order to synchronize the postregulator freewheeling
sequence to the forward converter demagnetization phase.
4 C_ramp The capacitor connected to the C_ramp pin enables to adjust the delay in turning on the highside
MOSFET (in conjunction with “I_ramp” current).
5 I_ramp The “I_ramp” pin receives a current supplied by a regulation means. This current adjusts the delay after
which the highside MOSFET is turned on. By this way, it modules the highside MOSFET on time in
order to regulate the output voltage.
6 V
DD
“V
DD
” is the power supply input. A 0.1 mF to 1.0 mF ceramic capacitor should be connected from this pin
to ground for decoupling.
7 LS_DRV “LS_DRV” is the driver output of the lowside MOSFET gate.
8 GND Ground.
NCP4330
http://onsemi.com
3
MAXIMUM RATINGS
Symbol Rating Value Unit
BST Bootstrap Input 0.3, +40 V
RST Reset Input 0.3, +5.0 V
C_ramp Timing Capacitor Node (Note 1) 0.3, V
rampHL
V
I_ramp Regulation Current Input (Note 1) 0.3, Vcl V
V
DD
Supply Voltage 0.3, +20 V
R
q
JA
Thermal Resistance 180 °C/W
T
J
Operating Junction Temperature Range (Note 2) 40, +125 °C
T
Jmax
Maximum Junction Temperature 150 °C
T
Smax
Storage Temperature Range 65 to +150 °C
T
Lmax
Lead Temperature (Soldering, 10 s) 300 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. V
rampHL
and Vcl are the internal clamp levels of pins 4 and 5 respectively.
2. The maximum junction temperature should not be exceeded.
ELECTRICAL CHARACTERISTICS (V
DD
= 10 V, V
BST
= 25 V, T
J
from 25°C to +125°C, unless otherwise specified.)
Symbol
Characteristic Min Typ Max Unit
HighSide Output Stage
V
HS_H
HighSide Output Voltage in High State @ Isource = 100 mA 22.5 23.5 V
V
HS_L
HighSide Output Voltage in Low State @ Isink = 100 mA 0.9 1.5 V
I
source_HS
Current Capability of the HighSide Drive Output in High State 0.5 A
I
sink_HS
Current Capability of the HighSide Drive Output in Low State 0.75 A
t
rHS
HighSide Output Voltage Rise Time from 0.5 V to 12 V (C
L
= 1.0 nF) 25 ns
t
fHS
HighSide Output Voltage Fall Time from 20 V to 0.5 V (C
L
= 1.0 nF) 25 ns
T
LSHS
Delay from LowSide Gate Drive Low (High) to HighSide Drive High (Low) 100 ns
LowSide Output Stage
V
LS_H
LowSide Output Voltage in High State @ Isource = 500 mA 7.4 8.2 V
V
LS_L
LowSide Output Voltage in Low State @ Isink = 750 mA 1.3 1.7 V
I
source_LS
Current Capability of the LowSide Drive Output in High State 0.5 A
I
sink_LS
Current Capability of the LowSide Drive Output in Low State 0.75 A
t
rLS
LowSide Output Voltage Rise Time from 0.5 V to 7.0 V (C
L
= 2.0 nF) 25 ns
t
fLS
LowSide Output Voltage Fall Time from 9.5 V to 0.5 V (C
L
= 2.0 nF) 25 ns
Ramp Control
I
charge
C_ramp Current
@ Ipin5 = 100 mA
@ Ipin5 = 1.5 mA
90
1400
102
1590
110
1800
mA
Vcl Pin5 Clamp Voltage @ Ipin5 = 1.5 mA 0.7 1.4 2.1 V
Vref
L
Ramp Control Reference Voltage, Vpin4 Falling 1.3 1. 5 1.7 V
Vref
H
Ramp Control Reference Voltage, Vpin4 Rising 2.25 2.5 2.75 V
V
rampHL
Ramp Voltage Maximum Value @ Ipin5 = 1.5 mA 3.2 3.6 4.2 V
V
rampLL
Ramp Voltage Low Voltage @ Ipin5 = 1.5 mA 100 mV

NCP4330DR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Gate Drivers Secondary Side Synchronous
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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