NCP4330
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13
HighSide Driver Stage
The highside turn on (turn off) is 100 ns delayed behind
the lowside turn off (turn on).
The highside drive is designed to drive on and off
12.5 nC gate charge power MOSFET, in 25 ns typical.
1. HighSide Turn On:
As portrayed by in figure 30, the highside turn on is a
“hard” switching (large dV/dt and dI/dt).
The necessary current capability is then:
I
hs * on
+
12.5 nC
25 ns
, that is 500 mA.
Figure 30. HighSide MOSFET Turn On
Time in Secs
Vin
lind
i(l1)
vin1
ihs
vdshs
hs_drv
I
Q
V
Q
40.0
20.0
0
20.0
40.0
ls_drv in volts
0
4.00
8.00
12.0
16.0
irl in amps
320
240
160
80.0
0
i(l1) in amps
0
20.0
40.0
60.0
80.0
vin1 in volts
8.00
4.00
0
4.00
8.00
v(vsn) in volts
HS_DRV
4.4990 M 4.4995 M 4.5000 M 4.5005 M 4.5010 M
NCP4330
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14
2. HighSide Turn Off:
The highside MOSFET turns in a very soft way (no
current, no voltage). The turn off drive is in fact designed to
face the high dV/dt that occurs when the MOSFET Q1
abruptly turns on. The current capability has been set to
750 mA so that a 30 V variation in 10 ns cannot parasitically
switch on a highside MOSFET exhibiting a 250 pF Crss.
4.5010 M 4.5015 M
4.5020 M
4.5025 M 4.5030 M
Figure 31. HighSide MOSFET Turn Off
Time in Secs
Vin
lind
i(l1)
vin1
ihs
vdshs
hs_drv
I
Q
V
Q
40.0
20.0
0
20.0
40.0
ls_drv in volts
0
4.00
8.00
12.0
16.0
irl in amps
320
240
160
80.0
0
i(l1) in amps
0
20.0
40.0
60.0
80.0
vin1 in volts
8.00
4.00
0
4.00
8.00
v(vsn) in volts
HS_DRV
3. Input Voltage Limitation:
Traditional highside drivers turn off the MOSFET they
control, by forcing nearly 0 V between gate and source. The
NCP4330 highside stage is not referenced to the MOSFET
source but to ground, and the HS MOSFET is forced off by
grounding its gate. This technique that saves the pin that is
traditionally connected to the MOSFET source, allows a
robust turn off of the power switch. In effect, the lowside
MOSFET that is ON when the highside is off, forces the
Highside MOSFET source to approximately 0 V.
However the highside MOSFET turn on is preceded by
a 100 ns phase during which both the lowside and
highside power switches are off. During this 100 ns phase,
the drain source voltage of the lowside MOSFET may get
high, given that in light load operation, the L2 coil current
may get negative and flow from the load toward the input
through the HS MOSFET body diode. In this case, the gate
source voltage of the highside MOSFET becomes negative
and substantially equal to the input voltage amplitude of the
postregulator in absolute value.
Therefore, the maximum value of the pulsed input
voltage should be chosen lower than the maximum
sourcegate voltage the HS MOSFET can sustain.
Traditional MOSFET Vgs maximum ratings are generally
+/20 V. Therefore, with this kind of MOSFETs, the input
voltage must keep below 20 V (possible spikes being
included).
Undervoltage Lockout
An undervoltage lockout comparator is incorporated to
guarantee that the device is fully functional before enabling
the output stages. The NCP4330 starts to operate when the
power supply V
DD
exceeds 5.8 V. A 600 mV hysteresis
avoids that some noise on the V
DD
might produce some
erratic turns on and off of the device. When the NCP4330
detects an undervoltage lockout condition, it keeps both the
highside and lowside drivers in low state.
The undervoltage lockout has a 4.9 V minimum threshold
(falling). As a consequence, around 3.4 V are available on
the driver outputs to force on the MOSFET. Such a level
allows to properly drive most MOSFETs.
NCP4330
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15
APPLICATIONS INFORMATION
Figure 32. Typical Application
The maximum value (V
M
) of the pulsed input voltage (V
IN
) must be kept lower than the maximum sourcegate voltage the HS MOSFET
can sustain
Q3
Q4
L2
INDUCTOR1
+
C4
D2
DIODE
C5
CAP
Vout
Regulation
Block
C2
CAP
R3
R4
10k
C_ramp (4)
I_ramp (5)
GND (8)
RST (3)
Q1
Q2
R1
R2
L1
INDUCTOR
+
C1
T1
TRANSFO
S1
SW
Forward
Control
Input Voltage
LOAD
TL431
R5
R6
C6
LOAD
OPTO1
DIODE_OPTO
OPTO1
NPNPHOTO
Buffer
AR2
Buffer
AR3
Current
Mirror
2.5V / 1.5V
Level
Shifter
U3
INVERTER
BandGap
UVD
Vref, UVDth
Comparator
Iramp
Iramp
(2) BST
(1) HS_DRV
(7) LS_DRV
RESET Block
HS_DRV and
LS_DRV low
+
U4
Hysteresis
C1
BST CAP
C5
CAP
S2
SW
T2
TRANS1
C7
CAPACITOR
C3
CAPACITOR
Buffer
Buffer
MC33152
D1
DIODE
R7
RES1
Active Clamp
U?
OR
Circuitry
V
DD
Undervoltage Detection
(UVD high if V
DD
<4.9 V)
V
DD
V
DD
V
DD
V
CC
V
out
V
DD
(6)
V
DD
V
IN
V
M
0 V

NCP4330DR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Gate Drivers Secondary Side Synchronous
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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