NCP4330
http://onsemi.com
10
Figure 25. High−Side MOSFET Duty Cycle vs. I_ramp
Conditions: Switching Frequency: 400 kHz, Reset Pulse
Duration: 250 ns, Switching Delay (between LS and HS):
100 ns, Cramp = 100 pF.
0
25
50
75
100
0 0.5 1.0 1.5 2.0 2.5
I_ramp (mA)
D (%)
One can note that the duty cycle increases when the
I_ramp current increases. The duty cycle is zero if the
I_ramp current is below about 110 μA.
The duty cycle is limited to about 81% mainly by the reset
time and the 100 ns delay that all together represent 14% of
the period. In a 100 kHz application, the relative impact of
these times would be reduced and the maximum duty cycle
would be higher (in the range of 92%).
In fact, the high−side on−times are useful only during the
forward on−times. Finally, if the duty cycle of the forward
converter is less than 80%, one can consider that the useful
post regulator duty cycle can vary between 0 and 100%.
It can also be noted that the HS MOSFET can be turned
on while the forward power switch is off, the forward
free−wheeling MOSFET (Q2) is on and then no voltage is
applied to the post−regulator. This is not an issue since the
MOSFETs Q2 and Q3 derive the L2 coil current so that the
free wheeling operation continues (refer to application
schematic).
However, such a situation should occur only during transient
phases. Should this state occur too frequently, an excessive
heating of the Q2 switch could be produced.
Figure 26. HS MOSFET Duty Cycle vs. I_ramp (zoom)
0
10
20
30
40
50
60
70
0 0.1 0.2 0.3 0.4 0.5 0.6
I_ramp (mA)
D (%)
RESET Block
The “reset” pin should receive the free−wheeling drive
signal of the forward (refer to application schematic). When
this voltage exceeds the reset block threshold (2.55 V
typically), the C_ramp capacitor is grounded by an internal
switch for about 250 ns and the low−side MOSFET is turned
on. The circuit is then initialized for a new cycle.
The voltage that is applied to the “reset” pin, may be
negative during one part of the period. The NCP4330
incorporates a negative clamp system to avoid that too
negative voltages on the pin may cause carriers injection
within the die. The negative clamp acts to force a minimum
voltage of about –0.3 V in conjunction with the external
resistor R3. It features a current capability of about 2.0 mA.
Figure 27. Reset Block
Q?
NPN
Negative
Clamp
RST pin
C_ramp
C
R3
1
2
3
AND
250 ns
RESET Pin
Vdelay
Vdelay
Ctrl
Ctrl
GND
250 ns
Voltage
HYST COMP
+
-
Reset signal
2.55 V/
1.55 V
V
DD
V
DD
To HS and LS drivers
