XA2C64A CoolRunner-II Automotive CPLD
DS553 (v1.1) May 5, 2007 www.xilinx.com 15
Product Specification
R
c. If done for too long, it can reduce the life of the
device.
7. Do not rely on the I/O states before the CPLD
configures. During power up, the CPLD I/Os may be
affected by internal or external signals.
8. Use a voltage regulator which can provide sufficient
current during device power up. As a rule of thumb, the
regulator needs to provide at least three times the peak
current while powering up a CPLD in order to guarantee
the CPLD can configure successfully.
9. Ensure external JTAG terminations for TMS, TCK, TDI,
TDO should comply with the IEEE 1149.1. All Xilinx
CPLDs have internal weak pull-ups on TDI, TMS, and
TCK.
10. Attach all CPLD V
CC
and GND pins in order to have
necessary power and ground supplies around the
CPLD.
11. Decouple all V
CC
and V
CCIO
pins with capacitors of
0.01 μF and 0.1 μF closest to the pins for each
V
CC
/V
CCIO
-GND pair.
12. Configure I/Os properly. CoolRunner-II Automotive
CPLDs have I/O banks; therefore, signals must be
assigned to appropriate banks (LVCMOS33,
LVCMOS18 …)
Recommendations
The following recommendations are for all automotive appli-
cations.
1. Use strict synchronous design (only one clocking event)
if possible. A synchronous system is more robust than
an asynchronous one.
2. Include JTAG stakes on the PCB. JTAG stakes can be
used to test the part on the PCB. They add benefit in
reprogramming part on the PCB, inspecting chip
internals with INTEST, identifying stuck pins, and
inspecting programming patterns (if not secured).
3. CoolRunner-II Automotive CPLDs work with any power
sequence, but it is preferable to power the V
CCI
(internal V
CC
) before the V
CCIO
for the applications in
which any glitches from device I/Os are unwanted.
4. Do not disregard report file warnings. Software
identifies potential problems when compiling, so the
report file is worth inspecting to see exactly how your
design is mapped onto the logic.
5. Understand the Timing Report. This report file provides
a speed summary along with warnings. Read the timing
file (*.tim) carefully. Analyze key signal chains to
determine limits to given clock(s) based on logic
analysis.
6. Review Fitter Report equations. Equations can be
shown in ABEL-like format, or can also be displayed in
Verilog or VHDL formats. The Fitter Report also
includes switch settings that are very informative of
other device behaviors.
7. Let design software define pinouts if possible. Xilinx
CPLD software works best when it selects the I/O pins
and manages resources for users. It can spread signals
around and improve pin-locking. If users must define
pins, plan resources in advance.
8. Perform a post-fit simulation for all speeds to identify
any possible problems (such as race conditions) that
might occur when fast-speed silicon is used instead of
slow-speed silicon.
9. Distribute SSOs (Simultaneously Switching Outputs)
evenly around the CPLD to reduce switching noise.
10. Terminate high speed outputs to eliminate noise caused
by very fast rising/falling edges.
Automotive Warranty Disclaimer
THIS WARRANTY DOES NOT EXTEND TO ANY IMPLEMENTATION IN AN APPLICATION OR ENVIRONMENT THAT IS
NOT CONTAINED WITHIN XILINX SPECIFICATIONS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE AND ARE
NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS. FURTHER, PRODUCTS ARE NOT WARRANTED
FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF THE VEHICLE UNLESS THERE IS A FAIL-SAFE OR
REDUNDANCY FEATURE AND ALSO A WARNING SIGNAL TO THE OPERATOR OF THE VEHICLE UPON FAILURE.
USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO APPLICABLE
LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY.
