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MICRF505YML-TR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42
Micrel MICRF505BML/YML
October 2006 13
M9999-103106
+1 408-944-0800
Values
Symbol Parameter
Min. Typ. Max.
Units
Tper Min. period of
SCLK
50 ns
Thigh Min. high time of
SCLK
20 ns
Tlow Min. low time of
SCLK
20 ns
tfall Max. time of
falling edge of
SCLK
1 µs
trise Max. time of rising
edge of SCLK
1 µs
Tcsr Max. time of rising
edge of CS to
falling edge of
SCLK
0 ns
Tcsf Min. delay from
rising edge of CS
to rising edge of
SCLK
5 ns
Twrite Min. delay from
valid IO to falling
edge of SCLK
during a write
operation
0 ns
Tread Min. delay from
rising edge of
SCLK to valid IO
during a read
operation
(assuming load
capacitance of IO
is 25pF)
75 ns
POR Power on Reset
delay from voltage
is supplied to he
device until POR
completed
4.6 9 ms
Table 6. Timing Specification for the 3-wire
Programming Interface
Power on Reset
When applying voltage to the MICRF505 a power on
reset state is entered. During the time period of
power on reset, the MICRF505 should be
considered to be in an unknown state and the user
should wait until completed (See Table 6). The
power on reset timing given in Table 6 is covering all
conditions and should be treated as a maximum
delay time. In some application it might be beneficial
to minimize the power on reset time. In these cases
we recommend to follow below procedure:
Program
address 0x00
Word:0x03
Read back
programmed
address 0x00
Value=0x03?
End of Power on
Reset
NO
YES
Micrel MICRF505BML/YML
October 2006 14
M9999-103106
+1 408-944-0800
Programming summary
• Use CS, SCLK, and IO to get access to the
control registers in MICRF505.
• SCLK is user-controlled.
• Write to the MICRF505 at positive edges
(MICRF505 reads at negative edges).
• Read from the MICRF505 at negative edges
(MICRF505 writes at positive edges)
• After power-on: Write to the complete set of
control registers.
• Address field is 7 bits long. Enter msb first.
• R/W bit is 1 bit long (“1” for read, “0” for
write)
• Address and R/W bit together make 1 octet
• All control registers are 8 bits long.
Enter/read msb in every octet first.
• Always write 8 bits to/read 8 bits from a
control register. This is the case for registers
with less than 8 used programming bits as
well.
• Writing: Bring CS high, write address and
R/W bit followed by the new values to fill into
the addressed control register(s) and bring
CS low for loading, i.e. activation of the new
control register values (“load_en” = 1).
• Reading: Bring CS high, write address and
R/W bit, set IO as an input, read present
contents of the addressed control
register(s), bring CS low and set IO an
output.
Micrel MICRF505BML/YML
October 2006 15
M9999-103106
+1 408-944-0800
Frequency Synthesizer
The MICRF505 frequency synthesizer consists of a
voltage-controlled oscillator (VCO), a crystal
oscillator, dual modulus prescaler, programmable
frequency dividers and a phase-detector. The loop-
filter is external for flexibility and can be a simple
passive circuit. The phase detector compares
frequencies of two signals and produces an error
signal which is proportional to the difference
between the input frequencies. The error signal is
used to control a voltage-controlled oscillator (VCO)
which creates an output frequency. The output
frequency is fed through a frequency divider back to
the input of the phase detector, producing a
feedback loop. If the output frequency drifts, the
error signal will increase, driving the frequency in the
opposite direction so as to reduce the error. Thus,
the output is locked to the frequency at the other
input. This input is called the reference and is
derived from a crystal oscillator, which is very stable
in frequency. The block diagram below shows the
basic elements and arrangement of a PLL-based
frequency synthesizer. The MICRF505 has a dual
modulus prescaler for increased frequency
resolution. In a dual modulus prescaler the main
divider is split into two parts, the main part N and an
additional divider A, where A < N. Both dividers are
clocked from the output of the dual-modulus
prescaler, but only the output of the N divider is fed
into the phase detector. The prescaler will first divide
by 16. Both N and A count down until A reaches
zero, at which point the prescaler is switched to a
division ratio 16+1. At this point, the divider N has
completed A counts. Counting continues until N
reaches zero, which is an additional N-A counts. At
this point the cycle repeats.
A6…A0 D7 D6 D5 D4 D3 D2 D1 D0
0001010 - - A0_5 A0_4 A0_3 A0_2 A0_1 A0_0
0001011 - - - - N0_11 N0_10 N0_9 N0_8
0001100 N0_7 N0_6 N0_5 N0_4 N0_3 N0_2 N0_1 N0_0
0001101 - - - - M0_11 M0_10 M0_9 M0_8
0001110 M0_7 M0_6 M0_5 M0_4 M0_3 M0_2 M0_1 M0_0
0001111 - - A1_5 A1_4 A1_3 A1_2 A1_1 A1_0
0010000 - - - - N1_11 N1_10 N1_9 N1_8
0010001 N1_7 N1_6 N1_5 N1_4 N1_3 N1_2 N1_1 N1_0
0010010 - - - - M1_11 M1_10 M1_9 M1_8
0010011 M1_7 M1_6 M1_5 M1_4 M1_3 M1_2 M1_1 M1_0
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42

MICRF505YML-TR

Mfr. #:
Buy MICRF505YML-TR
Manufacturer:
Microchip Technology / Micrel
Description:
RF Transceiver (contact local sales office)850MHz to 950MHz, 2.0V to 2.5V FSK Transceiver with +10dBm Power Amplifier
Lifecycle:
New from this manufacturer.
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