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MICRF505YML-TR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42
Micrel MICRF505BML/YML
October 2006 19
M9999-103106
+1 408-944-0800
Transceiver Sync/Non-Synchronous Mode
A6..A0 D7 D6 D5 D4 D3 D2 D1 D0
0000000 LNA_by PA2 PA1 PA0 Sync_en Mode1 Mode0 Load_en
0000110 - Mod_clkS2 Mod_clkS1 Mod_clkS0 BitSync_clkS2 BitSync_clkS1 BitSync_clkS0 BitRate_clkS2
0000111 BitRate_clkS1 BitRate_clkS0 RefClk_K5 RefClk_K4 RefClk_K3 RefClk_K2 RefClk_K1 RefClk_K0
Sync_en State Comments
0
Rx: Bit
synchronization off
Transparent reception of
data
0 Tx: DataClk pin off
Transparent transmission
of data
1
Rx: Bit
synchronization on
Bit-clock is generated by
transceiver
1 Tx: DATACLK pin on
Bit-clock is generated by
transceiver
When Sync_en = 1, it will enable the bit
synchronizer in receive mode. The bit synchronizer
clock needs to be programmed, see chapter Bit
synchronizer. The synchronized clock will be set out
on pit DATACLK.
In transmit mode, when Sync_en = 1, the clock
signal on pin DATACLK is a programmed bit rate
clock. Now the transceiver controls the actual data
rate. The data to be transmitted will be sampled on
rising edge of DATACLK. The micro controller can
therefore use the negative edge to change the data
to be transmitted. The clock used for this purpose,
BITRATE_CLK, is programmed in the same way as
the modulator clock and the bit synchronizer clock:
XCO
BITRATE_CLK
(7- )
f
f
Refclk_K 2
BitRate_clkS
=
⋅
where:
f
BITRATE_CLK
: The clock frequency used to
control the bit rate, should be equal to the bit
rate (bit rate of 20 kbit/sec requires a clock
requency of 20kHz)
f
XCO
: Crystal oscillator frequency
Refclk_K: 6 bit divider, values between 1
and 63
BitRate_clkS: Bit rate setting, values
between 0 and 6
Data Interface
The MICRF505 interface can be divided in to two
separate interfaces, a “programming interface” and a
“Data interface”. The “programming interface” has a
three wire serial programmable interface and is
described in chapter Programming.
The “data interface” can be programmed to sync-
/non-synchronous mode. In synchronous mode the
MICRF505 is defined as “Master” and provides a
data clock that allows users to utilize low cost micro
controller reference frequency.
The data interface is defined in such a way that all
user actions should take place on falling edge and is
illustrated Figure 9 and 10. The two figures illustrate
the relationship between DATACLK and DATAIXO
in receive mode and transmit mode.
MICRF505 will present data on rising edge and the
“USER” sample data on falling edge in receive
mode.
DATAIXO
DATACLK
Figure 10. Data interface in Receive Mode
The User presents data on falling edge and
MICRF505 samples on rising edge in transmit mode.
DATAIXO
DATACLK
Figure 11. Data interface in Transmit Mode
When entering transmit mode it is important to keep
DATAIXO in tri-state from the time Tx-mode is
entered until user starts sending data. The data is
provided directly to the modulation circuit and
violation of this may/will cause abnormal behavior.
Depending upon the chosen FSK modulation, some
sort of encoding might be needed. The different
modulation types and encoding is described in
chapter Frequency modulation.
Micrel MICRF505BML/YML
October 2006 20
M9999-103106
+1 408-944-0800
Receiver
The receiver is a zero intermediate frequency (IF)
type in order to make channel filtering possible with
low-power integrated low-pass filters. The receiver
consists of a low noise amplifier (LNA) that drives a
quadrature mixer pair. The mixer outputs feed two
identical signal channels in phase quadrature. Each
channel include a pre-amplifier, a third order Sallen-
Key RC lowpass filter from strong adjacent channel
signals and finally a limiter. The main channel filter is
a switched-capacitor implementation of a six-pole
elliptic lowpass filte. The elliptic filter minimizes the
total capacitance required for a given selectivity and
dynamic range. The cut-off frequency of the Sallen-
Key RC filter can be programmed to four different
frequencies: 100kHz, 150kHz, 230kHz and 340kHz.
The demodulator demodulates the I and Q channel
outputs and produces a digital data output. If detects
the relative phase of the I and Q channel signal. If
the I channel signal lags the Q channel, the FSK
tone frequency lies above the LO frequency (data
‘1’). If the I channel leads the Q channel, the FSK
tone lies below the LO frequency (data ‘0’). The
output of the receiver is available on the DataIXO
pin. A RSSI circuit (receive signal strength indicator)
indicates the received signal level.
Front End
A6..A0 D7 D6 D5 D4 D3 D2 D1 D0
0000000 LNA_by PA2 PA1 PA0 Sync_en Mode1 Mode0 Load_en
A low noise amplifier in RF receivers is used to
boost the incoming signal prior to the frequency
conversion process. This is important in order to
prevent mixer noise from dominating the overall
front-end noise performance. The LNA is a two-
stage amplifier and has a nominal gain of
approximately 23dB at 900MHz. The front end has a
gain of about 33dB to 35dB. The gain varies by 1-
1.5dB over a 2.0V to 2.5V variation in power supply.
The LNA can be bypassed by setting bit LNA_by to
‘1’. This can be useful for very strong input signal
levels. The front-end gain with the LNA bypassed is
about 9-10dB. The mixers have a going of about
10dB at 915MHz. The differential outputs of the
mixers can be made available at pins IchOut and
QchOut. The output impedance of each mixer is
about 8k
Ω.
The input impedance is close to 50
Ω as shown in
Figure 12, giving an input reflection of about -20dB.
The receiver does not require any matching network
to optimize the gain. However, a matching network is
recommended for harmonic suppression in Tx and
for improved selectivity in Rx.
Figure 12. LNA Input Impedance
Sallen-Key Filters
A6..A0 D7 D6 D5 D4 D3 D2 D1 D0
0000001 Modulation1 Modulation0 ‘0’ ‘0’ RSSI_en LD_en PF_FC1 PF_FC0
Each channel includes a pre-amplifier and a prefilter,
which is a three-pole Sallen-Key lowpass filter. It
protects the following switched-capacitor filter from
strong adjacent channel signals, and it also works as
an anti-aliasing filter. The preamplifier has a gain of
22-23dB. The maximum output voltage swing is
about 1.4Vpp for a 2.25V power supply. In addition,
the IF amplifier also performs offset cancellation.
Gain varies by less than 0.5dB over a 2.0 – 2.5V
variation in power supply. The third order Sallen-Key
lowpass filter is programmable to four different cut-
off frequencies according to the table below:
PF_FC1 PF_FC0 Cut-off Freq. (kHz)
0 0 100
0 1 150
1 0 230
1 1 340
Micrel MICRF505BML/YML
October 2006 21
M9999-103106
+1 408-944-0800
Switched Capacitor Filter
A6..A0 D7 D6 D5 D4 D3 D2 D1 D0
0001000 ‘1’ ‘1’ ScClk5 ScClk4 ScClk3 ScClk2 ScClk1 ScClk0
The main channel filter is a switched-capacitor
implementation of a six-pole elliptic low pass filter.
The elliptic filter minimized the total capacitance
required for a given selectivity and dynamic range.
The cut-off frequency of the switched-capacitor filter
is adjustable by changing the clock frequency.
The clock frequency is designed to be 20 times the
cut-off frequency. The clock frequency is derived
from the reference crystal oscillator. A
programmable 6-bit divider divides the frequency of
the crystal oscillator. To generate the correct non-
overlapping clock-phases needed by the filter this
frequency is then divided by 4. The cut-off frequency
of the filter is given by:
fCUT =
f
XCO
40 ⋅ ScClk
f
CUT
: Filter cutoff frequency
f
XCO
: Crystal oscillator frequency
ScClk: Switched capacitor filter clock, bits
ScClk5-0
For instance, for a crystal frequency of 16MHz and if
the 6 bit divider divides the input frequency by 4 the
cut-off frequency of the SC filter is 16MHz/(40 x 4) =
100kHz. 1
st
order RC low pass filters are connected
to the output of the SC filter-to-filter the clock
frequency.
The lowest cutoff frequency in the pre- and the main
channel filter must be set so that the received signal
is passed with no attenuation, which is frequency
deviation plus modulation. If there are any frequency
offset between the transmitter and the receiver, this
must also be taken into consideration. A formula for
the receiver bandwidth can be summarized as
follows:
fBW = + fOFFSET + fDEV + Baudrate / 2
where
f
BW
: Needed receiver bandwidth, fcut above
should not be smaller than f
BW
[Hz]
f
OFFSET
: Total frequency offset between
receiver and transmitter [Hz]
f
DEV
: Single-sided frequency deviation, see
chapter Modulator on how to calculate [Hz]
Baudrate: The baud rate given is bit/sec
RSSI
A6..A0 D7 D6 D5 D4 D3 D2 D1 D0
0000001 Modulation1 Modulation0 ‘0’ ‘0’ RSSI_en LD_en PF_FC1 PF_FC0
RSSI
33kohm, 1nF, 125kbps, BW=200kHz, Vdd=2.5V
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
-125 -115 -105 -95 -85 -75 -65 -55 -45 -35 -25
Pin [dBm]
RSSI [V]
Figure 13. RSSI Voltage
C10
1nF
R2
33k
Pin 14
RSSI
RS
SI
Figure 14. RSSI Network
A Typical plot of the RSSI voltage as function of
input power is shown in Figure 13. The RSSI has a
dynamic range of about 50dB from about -110dBm
to -60dBm input power.
The RSSI can be used as a signal presence
indicator. When a RF signal is received, the RSSI
output increases. This could be used to wake up
circuitry that is normally in a sleep mode
configuration to conserve battery life.
Another application for which the RSSI could be
used is to determine if transmit power can be
reduced in a system. If the RSSI detects a strong
signal, if could tell the transmitter to reduce the
transmit power to reduce current consumption.
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MICRF505YML-TR

Mfr. #:
Buy MICRF505YML-TR
Manufacturer:
Microchip Technology / Micrel
Description:
RF Transceiver (contact local sales office)850MHz to 950MHz, 2.0V to 2.5V FSK Transceiver with +10dBm Power Amplifier
Lifecycle:
New from this manufacturer.
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