LT5518
10
5518f
Some DACs use an output common mode voltage of 3.3V.
In that case, the interface circuit drawn in Figure 4 may be
used. The performance is very similar to the performance
of the DAC interface drawn in Figure 3, since the source
and load impedances of the lowpass ladder fi lter are both
200Ω differential and the current drive is the same. There
are some small differences:
The baseband drive capability cannot be improved using
an extra supply voltage, since the compliance range of
the DACs in Figure 4 is typically 3.3V – 0.5V to 3.3V +
0.5V, so its range has already been fully used.
G
DC
and f
–3dB
are a little different, since R3A (and R3B)
is 4.99k instead of 5.6k to accommodate the proper
DC level shift.
LO Section
The internal LO input amplifi er performs single-ended to
differential conversion of the LO input signal. Figure 5
shows the equivalent circuit schematic of the LO input.
The internal, differential LO signal is split into in-phase
and quadrature (90° phase shifted) signals that drive LO
buffer sections. These buffers drive the double balanced I
and Q mixers. The phase relationship between the LO input
and the internal in-phase LO and quadrature LO signals
is fi xed, and is independent of start-up conditions. The
phase shifters are designed to deliver accurate quadrature
signals for an LO frequency near 2GHz. For frequencies
signifi cantly below 1.8GHz or above 2.4GHz, the quadra-
ture accuracy will diminish, causing the image rejection
to degrade. The LO pin input impedance is about 50Ω,
and the recommended LO input power is 0dBm. For lower
LO input power, the gain, OIP2, OIP3 and dynamic range
will degrade, especially below –5dBm and at T
A
= 85°C.
For high LO input power (e.g. 5dBm), the LO feedthrough
will increase, without improvement in linearity or gain.
Harmonics present on the LO signal can degrade the image
rejection, because they introduce a small excess phase shift
in the internal phase splitter. For the second (at 4GHz) and
third harmonics (at 6GHz) at –20dBc level, the introduced
signal at the image frequency is about –55dBc or lower,
corresponding to an excess phase shift much less than 1
degree. For the second and third harmonics at –10dBc,
still the introduced signal at the image frequency is about
46dBc. Higher harmonics than the third will have less
impact. The LO return loss typically will be better than
14dB over the 1.7GHz to 2.4GHz range. Table 1 shows
the LO port input impedance vs frequency.
Figure 5. Equivalent Circuit Schematic of the LO Input
LO
INPUT
20pF
Z
IN
57
5518 F05
V
CC
C2
GND
3.3V
BBPI
BBMI
L1A
L1B
C1 C3
C4A
3.3nF
R4A
3.01k
R4B
3.01k
C4B
3.3nF
3.3V
DC
3.3V
DC
2.1V
DC
2.1V
DC
R3A
4.99k
R3B
4.99k
DAC
0mA TO
20mA
0mA TO
20mA
L2A
L2B
RF = 5.5dBm, MAX
5V
V
CC
C
GND
LOMI
LOPI
FROM
Q
5518 F04
BALUN
CM
V
REF
= 500mV
200
200
1.8pF
1.8pF
1.3k
1.3k
LT5518
Figure 4. LT5518 5th Order Filtered Baseband Interface with 3.3V
CM
DAC (Only I-Channel is Shown).
APPLICATIO S I FOR ATIO
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U
LT5518
11
5518f
Table 1. LO Port Input Impedance vs Frequency for EN = High
Frequency Input Impedance S
11
MHz Ω Mag Angle
1000 44.5 + j18.2 0.197 95
1400 60.3 + j6.8 0.112 30
1600 62.8 j0.6 0.113 2.4
1800 62.4 j9.0 0.136 32
2000 56.7 j15.6 0.157 58
2200 50.9 j16.5 0.161 77
2400 46.6 j15.2 0.159 94
2600 42.9 j13.9 0.165 109
The input impedance of the LO port is different if the part
is in shut-down mode. The LO input impedance for EN =
Low is given in Table 2.
Table 2. LO Port Input Impedance vs Frequency for EN = Low
Frequency Input Impedance S
11
MHz Ω Mag Angle
1000 42.1 + j43.7 0.439 75
1400 121 + j34.9 0.454 15
1600 134 j31.6 0.483 11
1800 91.3 j68.5 0.510 33
2000 56.4 j66.3 0.532 53
2200 37.7 j54.9 0.544 70
2400 27.9 j43.6 0.550 87
2600 22.1 j33.9 0.553 104
RF Section
After up-conversion, the RF outputs of the I and Q mixers are
combined. An on-chip balun performs internal differential
to single-ended output conversion, while transforming the
output signal impedance to 50Ω. Table 3 shows the RF
port output impedance vs frequency.
Table 3. RF Port Output Impedance vs Frequency for EN = High
and P
LO
= 0dBm
Frequency Input Impedance S
22
MHz Ω Mag Angle
1000 21.3 + j9.7 0.421 153
1400 29.8 + j20.3 0.348 121
1600 39.1 + j23.5 0.280 100
1800 50.8 + j18.4 0.180 77.1
2000 52.1 + j5.4 0.057 65.5
2200 43.2 j0.1 0.073 179
2400 36.0 + j2.0 0.164 171
2600 32.1 + j5.6 0.228 159
Figure 6. Equivalent Circuit Schematic of the RF Output
RF
OUTPUT
20pF
21pF 3nH
52.5
5518 F06
V
CC
The RF output S
22
with no LO power applied is given in
Table 4.
Table 4. RF Port Output Impedance vs Frequency for EN = High
and No LO Power Applied
Frequency Input Impedance S
22
MHz Ω Mag Angle
1000 21.7 + j9.9 0.416 153
1400 32.3 + j19.5 0.312 119
1600 42.2 + j18.5 0.214 102
1800 46.8 + j9.6 0.104 103
2000 41.8 + j3.7 0.098 154
2200 36.1 + j4.3 0.170 160
2400 32.8 + j7.4 0.226 152
2600 31.2 + j10.5 0.264 144
For EN = Low the S
22
is given in Table 5.
Table 5. RF Port Output Impedance vs Frequency for EN = Low
Frequency Input Impedance S
22
MHz Ω Mag Angle
1000 20.9+j9.6 0.428 154
1400 28.5 + j20.2 0.365 123
1600 36.7 + j24.5 0.311 103
1800 48.7 + j23.1 0.229 80.2
2000 55.7 + j11.0 0.116 56.7
2200 48.9 + j0.6 0.013 158.9
2400 39.8 j0.02 0.115 –179
2600 34.2 + j3.2 0.193 167
To improve S
22
for lower frequencies, a shunt capacitor
can be added to the RF output. At higher frequencies, a
shunt inductor can improve the S
22
. Figure 6 shows the
equivalent circuit schematic of the RF output.
Note that an ESD diode is connected internally from
the RF output to ground. For strong output RF signal
levels (higher than 3dBm) this ESD diode can degrade
the linearity performance if the 50Ω termination imped-
ance is connected directly to ground. To prevent this, a
APPLICATIO S I FOR ATIO
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U
LT5518
12
5518f
coupling capacitor can be inserted in the RF output line.
This is strongly recommended during a 1dB compression
measurement.
Enable Interface
Figure 7 shows a simplifi ed schematic of the EN pin inter-
face. The voltage necessary to turn on the LT5518 is 1.0V.
To disable (shutdown) the chip, the Enable voltage must
be below 0.5V. If the EN pin is not connected, the chip is
disabled. This EN = Low condition is guaranteed by the
75kΩ on-chip pull-down resistor. It is important that the
voltage at the EN pin does not exceed V
CC
by more than
0.5V. If this should occur, the full chip supply current could
be sourced through the EN pin ESD protection diodes.
Damage to the chip may result.
Figure 9. Demo Board Circuit Schematic
BBIPBBIM
J1
16 15 14 13
V
CC
V
CC
EN
9
10
11
12
4
3
2
1
5678
5518 F09
17
BBQM
BBQP
C4
100nF
J6
RF
OUT
J3
LO
IN
J4
GND
E3
E2
E1
J5
GND
E4
C6
3.3nF
C3
100nF
J2
BBMI
LT5518
BBPI V
CC
BBMQ GND
GND
BBPQ V
CC
GND
GND
RF
GND
GND
LO
GND
EN
GND
100
R7
R10
3.01k
R9
5.62k
R2
5.62k
R1
5.62k
R8
5.62k
R11
3.01k
R13
52.3
C2
3.3nF
R4
3.01k
R6
52.3
C5
3.3nF
R12
52.3
R3
3.01k
C1
3.3nF
R5
52.3
BOARD NUMBER: DC831A
Figure 10. Component Side Silk Screen of Demo Board
Evaluation and Demo Boards
Figure 8 shows the schematic of the evaluation board that
was used for the measurements summarized in the Elec-
trical Characteristics tables and the Typical Performance
Characteristic plots.
Figure 9 shows the demo board schematic. Resistors R3,
R4, R10 and R11 may be replaced by shorting wires if a
at frequency response to DC is required. A good ground
connection is required for the exposed pad of the LT5518
package. If this is not done properly, the RF performance
will degrade. The exposed pad also provides heat sink-
ing for the part and minimizes the possibility of the chip
overheating. R7 (optional) limits the Enable pin current in
the event that the Enable pin is pulled high while the V
CC
inputs are low. In Figures 10, 11 and 12 the silk screen
and the demo board PCB layouts are shown. If improved
LO and Image suppression is required, an LO feedthrough
calibration and an Image suppression calibration can be
performed.
Figure 7. EN Pin Interface
EN
75k
5518 F07
V
CC
25k
APPLICATIO S I FOR ATIO
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Figure 8. Evaluation Board Circuit Schematic
BBIPBBIM
J1
16 15 14 13
V
CC
V
CC
EN
9
10
11
12
4
3
2
1
5678
5518 F08
17
BBQM
BBQP
C1
100nF
J6
RF
OUT
J3
LO
IN
J4
GND
J5
C2
100nF
J2
BBMI
LT5518
BBPI V
CC
BBMQ GND
GND
BBPQ V
CC
GND
GND
RF
GND
GND
LO
GND
EN
GND
100
R1
BOARD NUMBER: DC729A

LT5518EUF#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Modulator / Demodulator 2GHz Direct Quadrature Modulator
Lifecycle:
New from this manufacturer.
Delivery:
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