LT5518
7
5518f
The LT5518 consists of I and Q input differential voltage-
to-current converters, I and Q up-conversion mixers, an
RF output balun, an LO quadrature phase generator and
LO buffers.
External I and Q baseband signals are applied to the dif-
ferential baseband input pins, BBPI, BBMI, and BBPQ,
BBMQ. These voltage signals are converted to currents and
translated to RF frequency by means of double-balanced
up-converting mixers. The mixer outputs are combined
Figure 1. Simplifi ed Circuit Schematic of the LT5518 (Only I-Half is Drawn)
in an RF output balun, which also transforms the output
impedance to 50Ω. The center frequency of the resulting
RF signal is equal to the LO signal frequency. The LO in-
put drives a phase shifter which splits the LO signal into
in-phase and quadrature LO signals. These LO signals
are then applied to on-chip buffers which drive the up-
conversion mixers. Both the LO input and RF output are
single-ended, 50Ω-matched and AC coupled.
90°
0°
LT5518
V-I
V-I
BALUN
V
CC
RF
LO
5518 BD
11
EN
1
396
GND
42
5
7
16
14
8 13
BBPI
BBMI
BBPQ
BBMQ
1715
GND
1210
RF
V
CC
= 5V
BBPI
BBMI
C
GND
LOMI
LOPI
FROM
Q
5518 F01
BALUN
CM
V
REF
= 500mV
200
200
1.8pF
1.8pF
1.3k
1.3k
LT5518
BLOCK DIAGRA
W
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LT5518
8
5518f
Baseband Interface
The baseband inputs (BBPI, BBMI), (BBPQ, BBMQ) pres-
ent a differential input impedance of about 2.9kΩ. At each
of the four baseband inputs, a lowpass fi lter using 200Ω
and 1.8pF to ground is incorporated (see Figure 1), which
limits the baseband bandwidth to approximately 250MHz
(–1dB point). The common mode voltage is about 2.06V
and is slightly temperature dependent. At T
A
= –40
o
C, the
common mode voltage is about 2.19V and at T
A
= 85
o
C
it is about 1.92V.
If the I/Q signals are DC-coupled to the LT5518, it is
important that the applied common mode voltage level
of the I and Q inputs is about 2.06V in order to properly
bias the LT5518. Some I/Q test generators allow setting
the common mode voltage independently. In this case, the
common mode voltage of those generators must be set
to 1.03V to match the LT5518 internal bias, because for
DC signals, there is no –6dB source-load voltage division
(see Figure 2).
Figure 2. DC Voltage Levels for a Generator Programmed at
1.03V
DC
for a 50Ω Load and for the LT5518 as a Load
DAC’s differential output current to minimize the LO to RF
feedthrough. Resistors R3A, R3B, R4A and R4B translate
the DAC’s output common mode level from about 0.5V
DC
to the LT5518’s input at about 2.06V
DC
. For these resis-
tors, 1% accuracy is recommended. For different ambi-
ent temperatures, the LT5518 input common mode level
varies with a temperature coeffi cient of about –2.7mV/°C.
The internal common mode feedback loop will correct
these level changes in order to bias the LT5518 at the
correct operating point. Resistors R3 and R4 are chosen
high enough that the LT5518 common mode compliance
current value will not be exceeded at the inputs of the
LT5518 as a result of temperature shifts. Capacitors C4A
and C4B minimize the input signal attenuation caused by
the network R3A, R3B, R4A and R4B. This results in a
gain difference between low frequency and high frequency
baseband signals. The high frequency baseband –3dB
corner point is approximately given by:
f
–3dB
= 1/[2π • C4A • (R3A||R4A||(R
IN, DIFF
/2)]
In this example, f
–3dB
= 58kHz.
This corner point should be set signifi cantly lower than the
minimum baseband signal frequency by choosing large
enough capacitors C4A and C4B. For signal frequencies
signifi cantly lower than f
–3dB
, the gain is reduced by ap-
proximately
G
DC
= 20 • log [R3A||(R
IN, DIFF
/2)]/[R3A||(R
IN, DIFF
/2)
+ R4A]
In this example, G
DC
= –11dB.
Inserting the network of R3A, R3B, R4A, R4B, C4A and
C4B has the following consequences:
Reduced LO feedthrough adjustment range. LO to RF
feedthrough can be reduced by adjusting the differential
DC offset voltage applied to the I and/or Q inputs. Be-
cause of the DC gain reduction, the range of adjustment
is reduced. The resolution of the offset adjustment is
improved by the same gain reduction factor.
DC notch for uneven number of channels. The interface
drawn in Figure 3 might not be practical for an uneven
number of channels, since the gain at DC is lower and
will appear in the center of (one of) the channel(s). In
that case, a DC-coupled level shifting circuit is required,
or the LT5528 might be a better solution.
5518 F02
1.5k50
LT5518GENERATOR
2.06V
DC
2.06V
DC
2.06V
DC
+
+
50
50
GENERATOR
2.06V
DC
1.03V
DC
+
The LT5518 should be driven differentially; otherwise, the
even-order distortion products will degrade the overall
linearity severely. Typically, a DAC will be the signal source
for the LT5518. A reconstruction fi lter should be placed
between the DAC output and the LT5518’s baseband
inputs. DC coupling between the DAC outputs and the
LT5518 baseband inputs is recommended. Active level
shifters may be required to adapt the common mode level
of the DAC outputs to the common mode input voltage
of the LT5518. It is also possible to achieve a DC level
shift with passive components, depending on the appli-
cation. For example, if fl at frequency response to DC is
not required, then the interface circuit of Figure 3 may be
used. This fi gure shows a commonly used 0mA – 20mA
DAC output followed by a passive 5th order lowpass
lter. The DC-coupled interface allows adjustment of the
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LT5518
9
5518f
Introduction of a (low frequency) time constant dur-
ing startup. For TDMA-like systems the time constant
introduced by C4A and C4B can cause some delay
during start-up. The associated time constant is ap-
proximately given by T
D
= R
IN, CM
• (C4A + C4B). In
this example it will result in a delay of about T
D
= 105
• 6.6n = 693ns.
The maximum sinusoidal single sideband RF output power
is about 5.5dBm for a full 0mA to 20mA DAC swing.
This maximum RF output level is usually limited by the
compliance voltage range of the DAC (V
COMPL
) which is
assumed here to be 1.25V. When the DAC output voltage
swing is larger than this compliance voltage, the baseband
signal will distort and linearity requirements usually will
not be met. The following situations can cause the DAC’s
compliance voltage limit to be exceeded:
1. Too high DAC load impedance. If the DC impedance to
ground is higher than V
COMPL
/I
MAX
= 1.25/0.02 = 62.5Ω,
the compliance voltage is exceeded for a full DAC swing. In
Figure 3, two 100Ω resistors in parallel are used, resulting
in a DC impedance to ground of 50Ω.
2. Too much DC offset. In some DACs, an additional DC
offset current can be set. For example, if the maximum
offset current is set to I
MAX
/8 = 2.5mA, then the maxi-
mum DC DAC load impedance to ground is reduced to
V
COMPL
/I
MAX
• (1 + 1/8) = 1.25/0.0225 = 55Ω.
3. DC shift caused by R3A, R3B, R4A and R4B if used. The
DC shift network consisting of R3A, R3B, R4A and R4B
Figure 3. LT5518 5th Order Filtered Baseband Interface with Common DAC (Only I-Channel is Shown)
will increase the voltage on the DAC output by dumping
an extra current into resistors R1A, R1B, R2A and R2B.
This current is about (V
CC
– V
DAC
)/(R3A + R4A) = (5
– 0.5)/(3.01k + 5.63k) = 0.52mA. Maximum impedance
to ground will then be V
COMPL
/(I
MAX
+ I
LS
) = 1.25/0.02052
= 60.9Ω.
4. Refl ection of out-of-band baseband signal power. DAC
output signal components higher than the cut-off frequency
of the lowpass fi lter will not see R2A and R2B as load
resistors and therefore will see only R1A, R1B and the
lter components as a load. Therefore, it is important to
start the lowpass fi lter with a capacitor (C1), in order to
shunt the DAC higher frequency components and thereby,
limit the required extra voltage headroom.
The LT5518’s output 1dB compression point is about
8.5dBm, and with the interface network described above,
a common DAC cannot drive the part into compression.
However, it is possible to increase the driving capability
by using a negative supply voltage. For example, if a –1V
supply is available, resistors R1A, R1B, R2A and R2B
can be made 200Ω each and connected with one side to
the –1V supply instead of ground. Typically, the voltage
compliance range of the DAC is –1V to 1.25V, so the DAC’s
output voltage will stay within this range. Almost 6dB extra
voltage swing is available, thus enabling the DAC to drive
the LT5518 beyond its 1dB compression point. Resistors
R3A, R3B, R4A, R4B and the lowpass fi lter components
must be adjusted for this case.
GND
C2
BBPI
BBMI
L1A
L1B
C1 C3
C4A
3.3nF
R4A
3.01k
R4B
3.01k
C4B
3.3nF
R1A
100
0.53V
DC
0.53V
DC
2.1V
DC
2.1V
DC
R1B
100
R2A
100
R2B
100
R3A
5.63k
R3B
5.63k
DAC
0mA TO 20mA
0mA TO 20mA
L2A
L2B
RF = 5.5dBm, MAX
5V
V
CC
C
GND
LOMI
LOPI
FROM
Q
5518 F03
BALUN
CM
V
REF
= 500mV
200
200
1.8pF
1.8pF
1.3k
1.3k
LT5518
APPLICATIO S I FOR ATIO
WUU
U

LT5518EUF#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Modulator / Demodulator 2GHz Direct Quadrature Modulator
Lifecycle:
New from this manufacturer.
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