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EFM32GG900F1024G-E-D1I

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27
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2016-03-21 - EFM32GG900FXX - d0280_Rev1.40 16
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Alternate LOCATION
Functionality 0 1 2 3 4 5 6 Description
TIM1_CC1 PC14 PE11 PB1 PB8 PD7 Timer 1 Capture Compare input / output channel 1.
TIM1_CC2 PC15 PE12 PB2 PB11 PC13 Timer 1 Capture Compare input / output channel 2.
TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0.
TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1.
TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2.
TIM3_CC0 PE14 PE0 Timer 3 Capture Compare input / output channel 0.
TIM3_CC1 PE15 PE1 Timer 3 Capture Compare input / output channel 1.
TIM3_CC2 PA15 PE2 Timer 3 Capture Compare input / output channel 2.
U0_RX PF7 PE1 PA4 PC15 UART0 Receive input.
U0_TX PF6 PE0 PA3 PC14
UART0 Transmit output. Also used as receive input in half
duplex communication.
U1_RX PC13 PF11 PB10 PE3 UART1 Receive input.
U1_TX PC12 PF10 PB9 PE2
UART1 Transmit output. Also used as receive input in half
duplex communication.
US0_CLK PE12 PE5 PC9 PC15 PB13 PB13 USART0 clock input / output.
US0_CS PE13 PE4 PC8 PC14 PB14 PB14 USART0 chip select input / output.
US0_RX PE11 PE6 PC10 PE12 PB8 PC1
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output
(MISO).
US0_TX PE10 PE7 PC11 PE13 PB7 PC0
USART0 Asynchronous Transmit.Also used as receive in-
put in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input
(MOSI).
US1_CLK PB7 PD2 PF0 USART1 clock input / output.
US1_CS PB8 PD3 PF1 USART1 chip select input / output.
US1_RX PC1 PD1 PD6
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output
(MISO).
US1_TX PC0 PD0 PD7
USART1 Asynchronous Transmit.Also used as receive in-
put in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input
(MOSI).
US2_CLK PC4 PB5 USART2 clock input / output.
US2_CS PC5 PB6 USART2 chip select input / output.
US2_RX PC3 PB4
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output
(MISO).
US2_TX PC2 PB3
USART2 Asynchronous Transmit.Also used as receive in-
put in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input
(MOSI).
USB_DM PF10 USB D- pin.
USB_DMPU PD2 USB D- Pullup control.
USB_DP PF11 USB D+ pin.
USB_ID PF12 USB ID pin. Used in OTG mode.
USB_VBUS USB_VBUS USB 5 V VBUS input.
USB_VBUSEN PF5 USB 5 V VBUS enable.
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Alternate LOCATION
Functionality 0 1 2 3 4 5 6 Description
USB_VREGI USB_VREGI USB Input to internal 3.3 V regulator
USB_VREGO USB_VREGO
USB Decoupling for internal 3.3 V USB regulator and reg-
ulator output
3.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32GG900 is shown in Table 3.3 (p. 17) . Each GPIO port is
organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated
by a number from 15 down to 0.
Table 3.3. GPIO Pinout
Port Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin
10
Pin
9
Pin
8
Pin
7
Pin
6
Pin
5
Pin
4
Pin
3
Pin
2
Pin
1
Pin
0
Port A PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
Port B PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
Port C PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
Port D PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0
Port F - - - PF12 PF11 PF10 PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0
3.4 Bonding Instructions
All pads should be bonded out, with the exception of the pads labeled “NC” and listed as “Do not connect”
in Table 3.1 (p. 5) . Gold bond wires are recommended for these devices.
All three voltage regulator output decouple pads (DEC_0, DEC_1, DEC_2) must be bonded out and
electrically connected on the PCB. In the packaged devices, these three pads are all bonded to a single
DECOUPLE pin.
If the USB feature of EFM32GG900 will be used, all of the USB pads must be bonded out, and
• both USB_VREGO_0 and USB_VREGO_1 must be bonded out and electrically connected on the
PCB. In the packaged devices, these two pads are both bonded to a single USB_VREGO pin.
• both USB_VREGI_0 and USB_VREGI_1 must be bonded out and electrically connected on the PCB.
In the packaged devices, these two pads are both bonded to a single USB_VREGI pin.
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3.5 Wafer Description
Table 3.4. Wafer and Die Information
Parameter Value
Device Family EFM32GG (Giant Gecko)
Wafer Diameter 8 in
Die Dimensions (Outer edge of seal ring) 6180 µm × 5230 µm
Wafer Thickness (No backgrind) 725 µm ±15 µm
(28.54 mil ±1 mil)
Wafer Identification Notch
Scribe Street Width 80 µm × 160 µm
Die Per Wafer
1
Contact sales for information
Passivation Standard
Wafer Packaging Detail Wafer Jar
Bond Pad Dimensions 65 µm (parallel to die edge) × 66 µm
Bond Pad Pitch Minimum 78 µm
Maximum Processing Temperature 250°C
Electronic Die Map Format .txt
1
Note: This is the Expected Known Good Die yielded per wafer and represents the batch order quantity (one wafer).
3.5.1 Environmental
Bare silicon die are susceptible to mechanical damage and may be sensitive to light. When bare die
must be used in an environment exposed to light, it may be necessary to cover the top and sides with
an opaque material.
For additional Quality and Environmental information, please see:
http://www.silabs.com/support/quality/pages/default.aspx.
3.6 Wafer Storage Guidelines
It is necessary to conform to appropriate wafer storage practices to avoid product degradation or con-
tamination.
• Wafers may be stored for up to 18 months in the original packaging supplied by Silicon Labs.
• Wafers must be stored at a temperature of 18 - 24 °C.
• Wafers must be stored in a humidity-controlled environment with a relative humidity of <30%
• Wafers should be stored in a clean, dry, inert atmosphere (e.g. nitrogen or clean, dry air).
3.7 Failure Analysis (FA) Guidelines
Certain conditions must be met for Silicon Laboratories to perform Failure Analysis on devices sold in
wafer form.
• In order to conduct failure analysis on a device in a customer-provided package, Silicon Laboratories
must be provided with die assembled in an industry standard package that is pin compatible with
existing packages Silicon Laboratories offers for the device. Initial response time for FA requests that
meet these requirements will follow the standard FA guidelines for packaged parts.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27

EFM32GG900F1024G-E-D1I

Mfr. #:
Buy EFM32GG900F1024G-E-D1I
Manufacturer:
Silicon Labs
Description:
IC MCU 32BIT 1MB FLASH WAFER
Lifecycle:
New from this manufacturer.
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