ISL6521CBZA-T Datasheet ISL6521CBZS2698, ISL6521IBZ, ISL6521CBZA-T | P4-P6

Absolute Maximum Ratings

UGATE, BOOT. . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 15V

VCC, PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +7V

DRIVE, LGATE, all other pins . . . . . . . . GND - 0.3V to VCC + 0.3V

Operating Conditions

Supply Voltage on VCC . . . . . . . . . . . . . . . . . . . . . . . . . . +5V 10%

Ambient Temperature Range

ISL6521CBZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

ISL6521IBZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C

Junction Temperature Range. . . . . . . . . . . . . . . . . . -40°C to 125°C

Thermal Information

Thermal Resistance (Typical, Note 1) 

(°C/W)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C

Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. 

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

Electrical Specifications Operating Conditions: VCC = 5V, T

= 0°C to 70°C, Unless Otherwise Noted. Typical specifications are at

= 25°C.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

VCC SUPPLY CURRENT

Nominal Supply Current I

UGATE, LGATE, and DRIVEx Open - 5 - mA

POWER-ON RESET

Rising VCC Threshold 4.25 - 4.51 V

Falling VCC Threshold 3.74 - 4.0 V

OSCILLATOR AND SOFT-START

Free Running Frequency F

OSC

ISL6521CBZ 275 300 325 kHz

ISL6521IBZ (-40°C to 85°C) 250 300 350 kHz

Ramp Amplitude V

OSC

-1.5- V

P-P

Soft-Start Interval T

6.25 6.83 7.40 ms

REFERENCE VOLTAGE

Reference Voltage (All Regulators) V

REF

0.780 0.800 0.820 V

All Outputs Voltage Regulation ISL6521CBZ -2.0 - +2.0 %

ISL6521IBZ (-40°C to 85°C) -2.5 - +2.5 %

LINEAR REGULATORS (OUT2, OUT3, AND OUT4)

Output Drive Current (All Linears) VCC > 4.5V 100 120 - mA

Undervoltage Level (V

REF

-70- %

SYNCHRONOUS PWM CONTROLLER ERROR AMPLIFIER

DC Gain -80- dB

Gain-Bandwidth Product GBWP 15 - - MHz

Slew Rate SR COMP = 10pF - 6 - V/s

PWM CONTROLLER GATE DRIVERS

UGATE Source I

UGATE

VCC = 5V, V

UGATE

= 2.5V - -1 - A

UGATE Sink I

UGATE

UGATE-PHASE

= 2.5V - 1 - A

LGATE Source I

LGATE

VCC = 5V, V

LGATE

= 2.5V - -1 - A

LGATE Sink I

LGATE

= 2.5V - 2 - A

PROTECTION

OCSET Current Source I

OCSET

ISL6521CBZ 34 40 46 A

ISL6521IBZ (-40°C to 85°C) 31.5 40 48 A

ISL6521

Functional Pin Descriptions

VCC (Pin 11)

Provide a well decoupled 5V bias supply for the IC to this

pin. This pin also provides the gate bias charge for the lower

MOSFET controlled by the PWM section of the IC, as well as

the drive current for the linear regulators. The voltage at this

pin is monitored for Power-On Reset (POR) purposes.

GND (Pin 5)

Signal ground for the controller. All voltage levels are

measured with respect to this pin.

PGND (Pin 9)

This is the power ground connection. Tie the source of the

lower MOSFET of the synchronous PWM converter to this

pin.

BOOT (Pin 7)

Floating bootstrap supply pin for the upper gate drive. The

bootstrap capacitor provides the necessary charge to turn

and hold the upper MOSFET on. Connect a suitable

capacitor (0.47F recommended) from this pin to PHASE.

OCSET (Pin 12)

Connect a resistor from this pin to the drain of the upper

PWM MOSFET. This resistor, an internal 40A current

source (typical), and the upper MOSFET’s on-resistance set

the converter overcurrent trip point. An overcurrent trip

cycles the soft-start function.

The voltage at this pin is monitored for power-on reset

(POR) purposes and pulling this pin below 1.25V with an

open drain/collector device will shut down the switching

controller.

PHASE (Pin 6)

Connect this pin to the source of the PWM converter upper

MOSFET. This pin is used to monitor the voltage drop across

the upper MOSFET for overcurrent protection.

UGATE (Pin 8)

Connect UGATE pin to the PWM converter’s upper

MOSFET gate. This pin provides the gate drive for the upper

MOSFET.

LGATE (Pin 10)

This pin provides the gate drive for the synchronous rectifier

lower MOSFET. Connect LGATE to the gate of the lower

MOSFET.

COMP and FB (Pins 4, 3)

COMP and FB are the available external pins of the PWM

converter error amplifier. The FB pin is the inverting input of the

error amplifier. Similarly, the COMP pin is the error amplifier

output. These pins are used to compensate the voltage-mode

control feedback loop of the synchronous PWM converter.

DRIVE2, 3, 4 (Pins 1, 15, 13)

Connect these pins to the point of load or to the base

terminals of external bipolar NPN transistors. These pins are

each capable of providing 120mA of load current or drive

current for the pass transistors.

FB2, 3, 4 (Pins 2, 16, 14)

Connect the output of the corresponding linear regulators to

these pins through properly sized resistor dividers. The

voltage at these pins is regulated to 0.8V. These pins are

also monitored for undervoltage events.

Quickly pulling and holding any of these pins above 1.25V

(using diode-coupled logic devices) shuts off the respective

regulators. Releasing these pins from the pull-up voltage

initiates a soft-start sequence on the respective regulator.

Description

Operation

The ISL6521 monitors and precisely controls one

synchronous PWM converter and three configurable linear

regulators from a +5V bias input. The PWM controller is

designed to regulate the core voltage of an embedded

processor or simple down conversion for high current

applications. The PWM controller drives two MOSFETs (Q1

and Q2) in a synchronous-rectified buck converter

configuration and regulates the output voltage to a level

programmed by a resistor divider. The linear controllers are

designed to regulate three additional system voltages.

Typically, these include any I/O, memory, or clock voltages

that might be required. All three linear controllers support

up to 120mA of load current without external pass devices

or higher currents with external NPN bipolar transistors.

Initialization

The ISL6521 automatically initializes upon receipt of input

power. The Power-On Reset (POR) function continually

monitors the input bias supply voltage. The POR monitors

the bias voltage at the VCC pin. The POR function initiates

soft-start operation after the bias supply voltage exceeds its

POR threshold.

Soft-Start

The POR function initiates the soft-start sequence. The

PWM error amplifier reference input is clamped to a level

proportional to the soft-start voltage. As the soft-start voltage

slews up, the PWM comparator generates PHASE pulses of

increasing width that charge the output capacitor(s).

Similarly, all linear regulators’ reference inputs are clamped

to a voltage proportional to the soft-start voltage. The ramp-

up of the internal soft-start function provides a controlled

output voltage rise.

Figure 1 shows the soft-start sequence for a typical

application. At T0 the +5V bias voltage starts to ramp up

crossing the 4.5V POR threshold at time T1. On the PWM

section, the oscillator’s triangular waveform is compared to

ISL6521

the clamped error amplifier output voltage. As the internal

soft-start voltage increases, the pulse-width on the PHASE

pin increases to reach its steady-state duty cycle at time T2.

Also at time T2, the error amplifier references of the linear

controllers, ramp to their final value bringing all outputs

within regulation limits.

Overcurrent Protection

All outputs are protected against excessive overcurrents.

The PWM controller uses the upper MOSFET’s

on-resistance, r

DS(ON)

to monitor the current for protection

against a shorted output. All linear controllers monitor their

respective FB pins for undervoltage events to protect against

excessive currents.

A sustained overload (undervoltage on linears or overcurrent

on the PWM) on any output results in an independent

shutdown of the respective output, followed by subsequent

individual re-start attempts performed at an interval equivalent

to 3 soft-start intervals. Figure 2 describes the protection

feature. At time T0, an overcurrent event sensed across the

switching regulator’s upper MOSFET (r

DS(ON)

sensing)

triggers a shutdown of the V

OUT1

output. As a result, its

internal soft-start initiates a number of soft-start cycles. After a

three-cycle wait, the fourth soft-start initiates a ramp-up

attempt of the failed output, at time T2, bringing the output in

regulation at time T4.

To exemplify a UV event on one of the linears, at time T1,

the clock regulator (V

OUT2

) is also subjected to an

overcurrent event, resulting in a UV condition. Similarly, after

three soft-start periods, the fourth cycle initiates a ramp-up of

this linear output at time T3. One soft-start period after T3,

the linear output is within regulation limits. UV glitches less

than 1s (typically) in duration are ignored.

Overcurrent protection is performed on the synchronous

switching regulator on a cycle-by-cycle basis. OC monitoring

is active as long as the regulator is operational. Since the

overcurrent protection on the linear regulators is performed

through undervoltage monitoring at the feedback pins (FB2,

FB3, and FB4), this feature is activated approximately 25%

into the soft-start interval (see Figure 2).

A resistor (R

OCSET

) programs the overcurrent trip level for

the PWM converter. As shown in Figure 3, the internal

40A current sink (I

OCSET

) develops a voltage across

OCSET

SET

) that is referenced to V

. The DRIVE

signal enables the overcurrent comparator (OCC). When

the voltage across the upper MOSFET (V

DS(ON)

) exceeds

SET

, the overcurrent comparator trips to set the

overcurrent latch. Both V

SET

and V

DS(ON)

are referenced

to V

and a small capacitor across R

OCSET

helps V

OCSET

track the variations of V

due to MOSFET switching. The

overcurrent function will trip at a peak inductor current

PEAK)

determined by:

FIGURE 1. SOFT-START INTERVAL

TIME

(0.5V/DIV)

OUT4

(3.3V)

OUT1

(1.5V)

T1 T2T0

(1V/DIV)

OUT3

(1.8V)

OUT2

(2.5V)

+5V

FIGURE 2. OVERCURRENT/UNDERVOLTAGE PROTECTION

RESPONSE

TIME

(0.5V/DIV.)

OUT3

(1.8V)

OUT2

(2.5V)

T1 T2

OUT4

(3.3V)

OUT1

(1.5V)

UV MONITORING

INACTIVE

SOFT-START

FUNCTION

ACTIVE

OUT2

OUT1

PEAK

OCSET



DS ON

----------------------------------------------------

ISL6521

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

ISL6521CBZA-T

Mfr. #:

Buy ISL6521CBZA-T

Manufacturer:

Renesas / Intersil

Description:

Switching Controllers W/ANNEAL 4 IN 1 PWM/ LINEAR CNTRLR 5V

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

ISL6521CBZA-T

ISL6521CBZA-T

Products related to this Datasheet