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ISL6521CBZA-T

P1-P3P4-P6P7-P9P10-P12P13-P13
7
The OC trip point varies with MOSFET’s r
DS(ON)
temperature variations. To avoid overcurrent tripping in the
normal operating load range, determine the R
OCSET
resistor from the equation above with:
1. The maximum r
DS(ON)
at the highest junction temperature.
2. The minimum I
OCSET
from the specification table.
3. Determine I
PEAK
for I
PEAK
> I
OUT(MAX)
+ (I)/2, where
I is the output inductor ripple current.
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
Output Voltage Selection
The output voltage of the PWM converter can be resistor-
programmed to any level between V
IN
and 0.8V. However,
since the value of R
S1
is affecting the values of the rest of
the compensation components, it is advisable its value is
kept between 2k and 5k.
Output voltage selection on the linear regulators is set by
means of external resistor dividers as shown in Figure 4.
The two resistors used to set the voltage on each of the
three linear regulators have to meet the following criteria:
their value while in a parallel connection has to be less than
5k, or otherwise said, the following relationship has to be
met:
To ensure the parallel combination of the feedback resistors
equals a certain chosen value, R
FB
, use the following
equations:
, where
V
OUT
- the desired output voltage,
V
FB
- feedback (reference) voltage, 0.8V.
Application Guidelines
Soft-Start Interval
The soft-start function controls the output voltages rate of rise
to limit the current surge at start-up. The soft-start function is
integrated on the chip and the soft-start interval is fixed.
PWM Controller Feedback Compensation
The PWM controller uses voltage-mode control for output
regulation. This section highlights the design consideration
for a PWM voltage-mode controller. Apply the methods and
considerations only to the PWM controller.
Figure 5 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
OUT
) is regulated to the reference voltage level, 0.8V. The
error amplifier (Error Amp) output (V
E/A
) is compared with
the oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of V
IN
at the
PHASE node. The PWM wave is smoothed by the output
filter (L
O
and C
O
).
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
E/A
. This function is dominated by a DC
Gain, given by V
IN
/V
OSC
, and shaped by the output filter,
with a double pole break frequency at F
LC
and a zero at
F
ESR
.
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6521) and the impedance networks Z
IN
UGATE
OCSET
PHASE
OCC
+
-
GATE
CONTROL
VCC
OC
40A
V
DS(ON)
i
D
V
SET
R
OCSET
V
IN
= +5V
OVERCURRENT TRIP:
I
OCSET
+
+
FIGURE 3. OVERCURRENT DETECTION
PWM
DRIVE
i
D
r
DS ON
¥I
OCSET
R
OCSET
¥>
V
DS
V
SET
>
V
PHASE
V
IN
V
DS
–=
V
OCSET
V
IN
V
SET
–=
DRIVE3
FB3
FB4
C
OUT4
C
OUT3
Q3
ISL6521
V
OUT3
V
OUT4
+5V
IN
DRIVE4
R
S3
R
P3
R
S4
R
P4
V
OUT
0.8 1
R
S
R
P
--------+



=
FIGURE 4. ADJUSTING THE OUTPUT VOLTAGE OF ANY OF
THE FOUR REGULATORS (OUTPUTS 3 AND 4
PICTURED)
+
+
R
S
R
P
R
S
R
P
+
----------------------
5k
R
S
V
OUT
V
FB
----------------
R
FB
=
R
P
R
S
V
FB
V
OUT
V
FB
–
---------------------------------
=
F
LC
1
2 L
O
C
O
----------------------------------------
=
F
ESR
1
2 ESR C
O
-----------------------------------------
=
ISL6521
8
and Z
FB
. The goal of the compensation network is to provide
a closed loop transfer function with high 0dB crossing
frequency (f
0dB
) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f
0dB
and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 5. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
ST
Zero Below Filter’s Double Pole (~75% F
LC
)
3. Place 2
ND
Zero at Filter’s Double Pole
4. Place 1
ST
Pole at the ESR Zero
5. Place 2
ND
Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Compensation Break Frequency Equations
Figure 6 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high
gain peak dependent on the quality factor (Q) of the output
filter, which is not shown in Figure 5. Using the above
guidelines should yield a Compensation Gain similar to the
curve plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at F
P2
with the capabilities of the error amplifier. The Closed Loop
Gain is constructed on the log-log graph of Figure 6 by
adding the Modulator Gain (in dB) to the Compensation Gain
(in dB). This is equivalent to multiplying the modulator
transfer function to the compensation transfer function and
plotting the gain.
The compensation gain uses external impedance networks
Z
FB
and Z
IN
to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Individual Output Disable
The PWM and linear controllers can independently be
shutdown.
To disable the switching regulator, use an open-drain or
open-collector device capable of pulling the OCSET pin (with
the attached R
OCSET
pull-up) below 1.25V. To minimize the
possibility of OC trips at levels different than predicted, a
C
OCSET
capacitor with a value of an order of magnitude
larger than the output capacitance of the pull-down device,
has to be used in parallel with R
OCSET
(1nF recommended).
Upon turn-off of the pull-down device, the switching regulator
undergoes a soft-start cycle.
To disable a particular linear controller, pull and hold the
respective FB pin above a typical threshold of 1.25V. One
way to achieve this task is by using a logic gate coupled
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
V
OUT
OSC
0.8V
L
O
C
O
ESR
V
IN
V
OSC
ERROR
AMP
PWM
DRIVER1
(PARASITIC)
Z
FB
+
-
0.8V
R
S1
R3
R2
C3
C2
C1
COMP
V
OUT
FB
Z
FB
ISL6521
Z
IN
COMP
DRIVER
DETAILED COMPENSATION COMPONENTS
PHASE
V
E/A
+
-
Z
IN
R
P1
SYNC
+
+
F
Z1
1
2 R 2C1
-----------------------------------
=
F
Z2
1
2 R
S1
R3+C3
----------------------------------------------------------
=
F
P1
1
2 R
2
C1 C2
C1 C2+
----------------------


-------------------------------------------------------
=
F
P2
1
2 R 3C3
-----------------------------------
=
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
100
80
60
40
20
0
-20
-40
-60
F
P1
F
Z2
10M1M100K10K1K10010
OPEN LOOP
ERROR AMP GAIN
F
Z1
F
P2
F
LC
F
ESR
COMPENSATION
GAIN (dB)
FREQUENCY (Hz)
GAIN
MODULATOR
GAIN
CLOSED LOOP
GAIN
20
V
IN
V
PP
------------



log
20
R2
R
S1
-------------



log
ISL6521
9
through a small-signal diode. The diode should be placed as
close to the FB pin as possible to minimize stray capacitance
to this pin. Upon turn-off of the pull-up device, the respective
output undergoes a soft-start cycle, bringing the output
within regulation limits. On regulators implementing this
feature, the parallel combination of the feedback resistors
has to be sufficiently high to allow ease of driving from the
external device. Considering the other restriction applying to
the upper range of this resistor combination (see ‘Output
Voltage Selection’ paragraph), it is recommended the values
of the feedback resistors on the linear regulator output meet
the following constraint:
Important Note When Using External Pass Devices
If the collector voltage to a linear regulator pass transistor
(Q3, Q4, or Q5 shown in Figure 7) is lost, the respective
regulator has to be shut down by pulling high its FB pin. This
measure is necessary in order to avoid possible damage to
the ISL6521 as a result of overheating. Overheating can
occur in such situations due to sheer power dissipation
inside the chip’s linear drivers.
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. The voltage
spikes can degrade efficiency, radiate noise into the circuit,
and lead to device overvoltage stress. Careful component
layout and printed circuit design minimizes the voltage
spikes in the converter. Consider, as an example, the turn-
off transition of the upper PWM MOSFET. Prior to turn-off,
the upper MOSFET was carrying the full load current.
During the turn-off, current stops flowing in the upper
MOSFET and is picked up by the lower MOSFET or
Schottky diode. Any inductance in the switched current
path generates a large voltage spike during the switching
interval. Careful component selection, tight layout of the
critical components, and short, wide circuit traces minimize
the magnitude of voltage spikes.
There are two sets of critical components in a DC-DC
converter using an ISL6521 controller. The switching power
components are the most critical because they switch large
amounts of energy, and as such, they tend to generate
equally large amounts of noise. The critical small signal
components are those connected to sensitive nodes or
those supplying critical bypass current.
The power components and the controller IC should be
placed first. Locate the input capacitors, especially the high-
frequency ceramic decoupling capacitors, close to the power
switches. Locate the output inductor and output capacitors
between the MOSFETs and the load. Locate the PWM
controller close to the MOSFETs.
The critical small signal components include the bypass
capacitor for VCC and the feedback resistors. Locate these
components close to their connecting pins on the control IC.
A multi-layer printed circuit board is recommended. Figure 7
shows the connections of the critical components in the
converter. Note that the capacitors C
IN
and C
OUT
each can
represent numerous physical capacitors. Dedicate one
solid layer for a ground plane and make all critical
component ground connections with vias to this layer.
Dedicate another solid layer as a power plane and break
this plane into smaller islands of common voltage levels.
The power plane should support the input power and
output power nodes. Use copper filled polygons on the top
and bottom circuit layers for the PHASE nodes, but do not
unnecessarily oversize these particular islands. Since the
PHASE nodes are subjected to very high dv/dt voltages,
the stray capacitor formed between these islands and the
surrounding circuitry will tend to couple switching noise.
Use the remaining printed circuit layers for small signal
wiring. The wiring traces from the control IC to the
MOSFET gate and source should be sized to carry 2A peak
currents.
2k
R
S
R
P
R
S
R
P
+
----------------------
5k
FIGURE 7. PRINTED CIRCUIT BOARD POWER PLANES AND
ISLANDS
V
OUT1
Q1
Q2
Q3
Q4
+12V
C
VCC
VIA CONNECTION TO GROUND PLANE
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT OR POWER PLANE LAYER
L
OUT
C
OUT1
CR1
ISL6521
C
IN
C
OUT2
V
OUT2
V
OUT3
+5V
IN
PGND
LGATE
UGATE
PHASE
DRIVE3
KEY
GNDVCC
DRIVE2
OCSET
R
OCSET
C
OCSET
LOAD
V
OUT4
DRIVE4
+3.3V
IN
L
IN
Q5
C
OUT3
C
OUT4
LOAD
LOAD
LOAD
+
+
+
+
+
ISL6521
P1-P3P4-P6P7-P9P10-P12P13-P13

ISL6521CBZA-T

Mfr. #:
Buy ISL6521CBZA-T
Manufacturer:
Renesas / Intersil
Description:
Switching Controllers W/ANNEAL 4 IN 1 PWM/ LINEAR CNTRLR 5V
Lifecycle:
New from this manufacturer.
Delivery:
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