CY28346ZXC-2 Datasheet CY28346ZI-2T, CY28346ZI-2, CY28346ZXC-2T | P10-P12

CY28346-2

......................Document #: 38-07509 Rev. *B Page 10 of 19

Three-state Control of CPU Clocks Clarification

During CPU_STP# and PD# modes, CPU clock outputs may

be set to driven or undriven (three-state) by setting the corre-

sponding SMBus entry in Bit6 of Byte0 and Bit6 of Byte1.

PCI_STP# Assertion

The PCI_STP# signal is an active LOW input used for

synchronous stopping and starting the PCI outputs while the

rest of the clock generator continues to function. The set-up

time for capturing PCI_STP# going LOW is 10 ns (t

setup

). (See

Figure 2.) The PCIF (0:2) clocks will not be affected by this pin

if their control bits in the SMBus register are set to allow them

to be free running.

PCI_STP# Deassertion

The deassertion of the PCI_STP# signal will cause all PCI and

stoppable PCIF clocks to resume running in a synchronous

manner within two PCI clock periods after PCI_STP# transi-

tions to a high level.

Note that the PCI STOP function is controlled by two inputs.

One is the device PCI_STP# pin number 34 and the other is

SMBus byte 0 bit 3. These two inputs to the function are

logically ANDed. If either the external pin or the internal

SMBus register bit is set low then the stoppable PCI clocks will

be stopped in a logic low state. Reading SMBus Byte 0 Bit 3

will return a 0 value if either of these control bits are set LOW

thereby indicating the devices stoppable PCI clocks are not

running.

Table 6. Cypress Clock Power Management Truth Table

B0b6 B1b6 PD# CPU_STP# Stoppable CPUT

Stoppable

CPUC Non-Stop CPUT Non-Stop CPUC

0 0 1 1 Running Running Running Running

0 0 1 0 Iref x6 Iref x6 Running Running

0 0 0 1 Iref x2 Low Iref x2 Low

0 0 0 0 Iref x2 Low Iref x2 Low

0 1 1 1 Running Running Running Running

0 1 1 0 Hi Z Hi Z Running Running

0 1 0 1 Hi Z Hi Z Hi Z Hi Z

0 1 0 0 Hi Z Hi Z Hi Z Hi Z

1 0 1 1 Running Running Running Running

1 0 1 0 Iref x6 Iref x6 Running Running

1 0 0 1 Hi Z Hi Z Hi Z Hi Z

1 0 0 0 Hi Z Hi Z Hi Z Hi Z

1 1 1 1 Running Running Running Running

1 1 1 0 Hi Z Hi Z Running Running

1 1 0 1 Hi Z Hi Z Hi Z Hi Z

1 1 0 0 Hi Z Hi Z Hi Z Hi Z

PCI_STP#

PCIF 33M

PCI 33M

setup

Figure 6. PCI_STP# Assertion Waveforms

CY28346-2

......................Document #: 38-07509 Rev. *B Page 11 of 19

Iout is selectable depending on implementation. The param-

eters above apply to all configurations. Vout is the voltage at

the pin of the device.

The various output current configurations are shown in the

host swing select functions table. For all configurations, the

deviation from the expected output current is ±7% as shown in

the current accuracy table.

PCI_STP#

PCIF

PCI

setup

Figure 7. PCI_STP# Deassertion Waveforms

Figure 8. VTT_PWRGD# Timing Diagram

VID

SEL

VTT_PWRGD#

PWRGD

VDD Clock Gen

Clock State

Clock Outputs

Clock VCO

0.2-0.3mS

Delay

State 0

State 2 State 3

Wait for

VTT_PWRGD#

Sample Sels

Off

State 1

Device is not affected,

VTT_PWRGD# is ignored.

VTT_PWRGD# = Low

Delay

>0.25mS

Power Off

VDDA = 2.0V

Sample

Inputs straps

Normal

Operation

Wait for <1.8ms

Enable Outputs

VTT_PWRGD# = toggle

VDD3.3= off

Figure 9. Clock Generator Power-up/Run State Program

CY28346-2

......................Document #: 38-07509 Rev. *B Page 12 of 19

USB and DOT 48M Phase Relationship

The 48M_USB and 48M_DOT clocks are in phase. It is under-

stood that the difference in edge rate will introduce some in

inherent offset. When 3V66_1/VCH clock is configured for

VCH (48-MHz) operation it is also in phase with the USB and

DOT outputs. See

Figure 10.

66IN to 66B Buffered Prop Delay

The 66IN to 66B(0:2) output delay is shown in Figure 11.

The Tpd is the prop delay from the input pin (66IN) to the

output pins (66B[0:2]). The outputs’ variation of Tpd is

described in the AC parameters section of this data sheet. The

measurement is taken at 1.5V.

66B to PCI Buffered Clock Skew

Figure 12 shows the difference (skew) between the 3V33(0:5)

outputs when the 66M clocks are connected to 66IN. This

offset is described in the Group Timing Relationship and Toler-

ances section of this data sheet. The measurements were

taken at 1.5V.

3V66 to PCI Unbuffered Clock Skew

Figure 13 shows the timing relationship between 3V66(0:5)

and PCI(0:6) and PCIF when configured to run in the unbuf-

fered mode.

Table 7. Host Clock (HCSL) Buffer Characteristics

Characteristic Minimum Maximum

Ro 3000 Ohms (recommended) N/A

Ros

Vout N/A 1.2V

Table 8. CPU Clock Current Select Function

Mult0 Board Target Trace/Term Z Reference R, Iref – Vdd (3*Rr) Output Current Voh @ Z

0 50 Ohms Rr = 221 1%, Iref = 5.00 mA Ioh = 4*Iref 1.0V @ 50

1 50 Ohms Rr = 475 1%, Iref = 2.32 mA Ioh = 6*Iref 0.7V @ 50

Table 9. Group Timing Relationship and Tolerances

Description Offset Tolerance Conditions

3V66 to PCI 2.5 ns 1.0 ns 3V66 Leads PCI (unbuffered mode)

48M_USB to 48M_DOT Skew 0.0 ns

1.0 ns 0 degrees phase shift

66B to PCI offset 2.5 ns

1.0 ns 66B leads PCI (buffered mode)

Table 10.Maximum Lumped Capacitive Output Loads

Clock Max Load Unit

PCI Clocks 30 pF

3V66 30 pF

66B 30 pF

48M_USB Clock 20 pF

48M_DOT 10 pF

REF Clock 50 pF

48MUSB

48MDOT

Figure 10. 48M_USB and 48M_DOT Phase Relationship

66IN

66B

Tpd

Figure 11. 66IN to 66B(0:2) Output Delay Figure

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

CY28346ZXC-2

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Clock Synthesizer / Jitter Cleaner NB Clk Intel Brkdale 830M & 845 chipsets

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