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CY28346ZXC-2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
CY28346-2
........................Document #: 38-07509 Rev. *B Page 4 of 19
Byte 0: CPU Clock Register
Bit @Pup Name Description
7 0 Spread Spectrum Enable, 0 = Spread Off, 1 = Spread On. This is a Read and Write control bit.
60
CPU clock Power-down Mode Select.
0 = Drive CPUT(0:2) to 4 or 6 IREF and drive CPUC(0:2) to low when PD# is asserted LOW.
1 = Three-state all CPU outputs. This is only applicable when PD# is LOW. It is not applicable to
CPU_STP#.
50
3V66_1/VCH 3V66_1/VCH frequency Select, 0 = 66M selected, 1 = 48M selected
This is a Read and Write control bit.
4 Pin 53 CPUT,CPUC CPU_STP#. Reflects the current value of the external CPU_STP# (pin 53) This bit is Read-only.
3Pin 34
PCI Reflects the current value of the internal PCI_STP# function when read. Internally PCI_STP# is
a logical AND function of the internal SMBus register bit and the external PCI_STP# pin.
2 Pin 40 Frequency Select Bit 2. Reflects the value of SEL2 (pin 40). This bit is Read-only.
1 Pin 55 Frequency Select Bit 1. Reflects the value of SEL1 (pin 55). This bit is Read-only.
0 Pin 54 Frequency Select Bit 0. Reflects the value of SEL0 (pin 54). This bit is Read-only.
Byte 1
: CPU Clock Register
Bit @Pup Name Description
7 Pin 43 MULT0 MULT0 (Pin 43) Value. This bit is Read-only.
6 0 CPU_STP#
Controls functionality of CPUT/C(0:2) outputs when CPU_STP# is asserted. 0 = Drive CPUT(0:2) to
4 or 6 IREF and drive CPUC(0:2) to low when CPU_STP# asserted LOW. 1 = Three-state all CPU
outputs. This bit will override Byte0, Bit6 such that even if it is a 0, when PD# goes low the CPU outputs
will be three-stated.
50
CPUT2
CPUC2
Controls CPU2 functionality when CPU_STP# is asserted LOW
1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW
This is a Read and Write control bit.
40
CPUT1
CPUC1
Controls CPU1 functionality when CPU_STP# is asserted LOW
1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW
This is a Read and Write control bit.
30
CPUT0
CPUC0
Controls CPUT0 functionality when CPU_STP# is asserted LOW
1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW
This is a Read and Write control bit.
21
CPUT2
CPUC2
CPUT/C2 Output Control, 1 = enabled, 0 = disable HIGH and CPUC2 disables LOW
This is a Read and Write control bit.
11
CPUT1
CPUC1
CPUT/C1 Output Control, 1 = enabled, 0 = disable HIGH and CPUC1 disables LOW
This is a Read and Write control bit.
01
CPUT0
CPUC0
CPUT/C0 Output Control, 1 = enabled, 0 = disable HIGH and CPUC0 disables LOW
This is a Read and Write control bit.
Byte 2
: PCI Clock Control Register (all bits are read and write functional)
Bit @Pup Name Description
7 0 REF REF Output Control. 0 = high strength, 1 = low strength
6 1 PCI6 PCI6 Output Control. 1 = enabled, 0 = forced LOW
5 1 PCI5 PCI5 Output Control. 1 = enabled, 0 = forced LOW
4 1 PCI4 PCI4 Output Control. 1 = enabled, 0 = forced LOW
3 1 PCI3 PCI3 Output Control. 1 = enabled, 0 = forced LOW
2 1 PCI2 PCI2 Output Control. 1 = enabled, 0 = forced LOW
1 1 PCI1 PCI1 Output Control. 1 = enabled, 0 = forced LOW
0 1 PCI0 PCI0 Output Control. 1 = enabled, 0 = forced LOW
CY28346-2
........................Document #: 38-07509 Rev. *B Page 5 of 19
Byte 3: PCIF Clock and 48M Control Register (all bits are read and write functional)
Bit @Pup Name Description
7 1 48M_DOT 48M_DOT Output Control,1 = enabled, 0 = forced LOW
6 1 48M_USB 48M_USB Output Control,1 = enabled, 0 = forced LOW
5 0 PCIF2 PCI_STP#, control of PCIF2.
0 = Free Running, 1 = Stopped when PCI_STP# is LOW
4 0 PCIF1 PCI_STP#, control of PCIF1.
0 = Free Running, 1 = Stopped when PCI_STP# is LOW
3 0 PCIF0 PCI_STP#, control of PCIF0.
0 = Free Running, 1 = Stopped when PCI_STP# is LOW
2 1 PCIF2 PCIF2 Output Control. 1=running, 0=forced LOW
1 1 PCIF1 PCIF1 Output Control. 1= running, 0=forced LOW
0 1 PCIF0 PCIF0 Output Control. 1= running, 0=forced LOW
Byte 4
: DRCG Control Register(all bits are read and write functional)
Bit @Pup Name Description
7 0 SS2 Spread Spectrum control bit (0 = down spread, 1 = center spread)
60 Reserved
5 1 3V66_0 3V66_0 Output Enabled. 1 = enabled, 0 = disabled
4 1 3V66_1/VCH 3V66_1/VCH Output Enable. 1 = enabled, 0 = disabled
3 1 3V66_5 3V66_5 Output Enable. 1 = enabled, 0 = disabled
2 1 66B2/3V66_4 66B2/3V66_4 Output Enabled. 1 = enabled, 0 = disabled
1 1 66B1/3V66_3 66B1/3V66_3 Output Enabled. 1 = enabled, 0 = disabled
0 1 66B0/3V66_2 66B0/3V66_2 Output Enabled. 1 = enabled, 0 = disabled
Byte 5
: Clock Control Register (all bits are read and write functional)
Bit @Pup Name Description
7 0 SS1 Spread Spectrum control bit
6 1 SS0 Spread Spectrum control bit
5 0 66IN to 66M delay Control MSB
4 0 66IN to 66M delay Control LSB
30 Reserved
2 0 48M_DOT edge rate control. When set to 1, the edge is slowed by 15%.
10 Reserved
0 0 USB edge rate control. When set to 1, the edge is slowed by 15%
Byte 6
: Silicon Signature Register
[2]
(all bits are read-only)
Bit @Pup Name Description
70
60
50
41
3 0 Vendor Code, 011 = IMI
20
11
01
Note:
2. When writing to this register the device will acknowledge the write operation, but the data itself will be ignored.
CY28346-2
........................Document #: 38-07509 Rev. *B Page 6 of 19
Dial-a-Frequency Feature
SMBus Dial-a-Frequency feature is available in this device via
Byte8 and Byte9. See our App Note AN-0025 for details on our
Dial-a-Frequency feature.
P is a large value PLL constant that depends on the frequency
selection achieved through the hardware selectors (S1, S0).
P value may be determined from Table 3.
Dial-a-dB Features
SMBus Dial-a-dB feature is available in this device via Byte8
and Byte9.
Spread Spectrum Clock Generation (SSCG)
Spread Spectrum is a modulation technique used to
minimizing EMI radiation generated by repetitive digital
signals. A clock presents the greatest EMI energy at the center
frequency it is generating. Spread Spectrum distributes this
energy over a specific and controlled frequency bandwidth
therefore causing the average energy at any one point in this
band to decrease in value. This technique is achieved by
modulating the clock away from its resting frequency by a
certain percentage (which also determines the amount of EMI
reduction). In this device, Spread Spectrum is enabled by
setting specific register bits in the SMBus control Bytes.
Table 4 is a listing of the modes and percentages of Spread
Spectrum modulation that this device incorporates.
Byte 7
: Watchdog Time Stamp Register
Bit @Pup Name Description
70 Reserved
60 Reserved
50 Reserved
40 Reserved
30 Reserved
20 Reserved
10 Reserved
00 Reserved
Byte 8
: Dial-a-Frequency Control Register N (all bits are read and write functional)
Bit @Pup Name Description
70 N7, MSB
60 N6
50 N5
40 N4
30 N3
20 N2
10 N3
00 N0, LSB
Byte 9
: Dial-a-Frequency Control Register R (all bits are read and write functional)
Bit @Pup Name Description
70 R6 MSB
60 R5
50 R4
40 R3
30 R2
20 R1
10 R0, LSB
0 0 R and N register load gate 0 = gate closed (data is latched), 1 = gate open
(data is loading from SMBus registers into R and N)
Table 3. P Value
S(1:0) P
0 0 32005333
0 1 48008000
1 0 96016000
1 1 64010667
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

CY28346ZXC-2

Mfr. #:
Buy CY28346ZXC-2
Manufacturer:
Silicon Labs
Description:
Clock Synthesizer / Jitter Cleaner NB Clk Intel Brkdale 830M & 845 chipsets
Lifecycle:
New from this manufacturer.
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