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......................Document #: 38-07509 Rev. *B Page 13 of 19
Buffer Characteristics
Current Mode CPU Clock Buffer Characteristics
The current mode output buffer detail and current reference
circuit details are contained in the previous table of this data
sheet. The following parameters are used to specify output
buffer characteristics:
1. Output impedance of the current mode buffer circuit – Ro
(see
Figure 14).
2. Minimum and maximum required voltage operation range
of the circuit – Vop (see
Figure 14).
3. Series resistance in the buffer circuit – Ros (see
Figure 14).
4. Current accuracy at given configuration into nominal test
load for given configuration.
66B
PCI
PCIF
1.5-
3.5ns
Figure 12. Buffer Mode – 33V66(0:1); 66BUF(0:2) Phase Relationship
PCI
PCIF
Tpci
3V66
Figure 13. Unbuffered Mode – 3V66(0:5) to PCI (0:6) and PCIF(0:2) Phase Relationship
1.2V0V
Iout
Iout
Ros
Ro
VDD3 (3.3V +/- 5%)
Vout = 1.2V max Vout
Slope ~ 1/R
0
Figure 14.
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......................Document #: 38-07509 Rev. *B Page 14 of 19
Absolute Maximum Conditions
Parameter Description Condition Min. Max. Unit
V
DD
Core Supply Voltage –0.5 4.6 V
V
DD_A
Analog Supply Voltage –0.5 4.6 V
V
IN
Input Voltage Relative to V
SS
–0.5 V
DD
+ 0.5 VDC
T
S
Temperature, Storage Non-functional –65 150 °C
T
A
Temperature, Operating Ambient Functional 0 85 °C
T
J
Temperature, Junction Functional 150 °C
Ø
JC
Dissipation, Junction to Case Mil-Spec 883E Method 1012.1 45 °C/W
Ø
JA
Dissipation, Junction to Ambient JEDEC (JESD 51) 15 °C/W
ESD
HBM
ESD Protection (Human Body Model) MIL-STD-883, Method 3015 2000 V
Ul-94 Flammability Rating V–0 @1/8 in. 10 ppm
MSL Moisture Sensitivity Level 1
DC Parameters (V
DD
= V
DDA
= 3.3V ±5%)
Parameter Description Conditions Min. Typ. Max. Unit
Idd3.3V Dynamic Supply Current All frequencies at maximum values
[3]
280 mA
Ipd3.3V Power-down Supply Current PD# Asserted Note 4 mA
Cin Input Pin Capacitance 5pF
Cout Output Pin Capacitance 6pF
Lpin Pin Inductance 7nH
Cxtal Crystal Pin Capacitance Measured from the Xin or Xout Pin to Ground. 30 36 42 pF
AC Parameters (V
DD
= V
DDA
= 3.3V ±5%)
Parameter Description
66 MHz 100 MHz 133 MHz 200 MHz
Unit NotesMin. Max. Min. Max. Min. Max. Min. Max.
Crystal
Tdc Xin Duty Cycle 47.5 52.5 47.5 52.5 47.5 52.5 47.5 52.5 % 5, 6, 7
Tperiod Xin Period 69.84 71.0 69.84 71.0 69.84 71.0 69.84 71.0 ns 5, 8, 9, 6
Vhigh Xin High Voltage 0.7Vdd Vdd 0.7Vdd Vdd 0.7Vdd Vdd 0.7Vdd Vdd V
Vlow Xin Low Voltage 0 0.3Vdd 0 0.3Vdd 0 0.3Vdd 0 0.3Vdd V
Tr/Tf Xin Rise and Fall
Times
10.0 10.0 10.0 10.0 ns 10
Tccj Xin Cycle to Cycle
Jitter
500 500 500 500 ps 8, 11, 6
CPU at 0.7V Timing
Tdc CPUT and CPUC
Duty Cycle
45 55 45 55 45 55 45 55 % 11, 12, 13
Tperiod CPUT and CPUC
Period
14.85 15.3 9.85 10.2 7.35 7.65 4.85 5.1 ns 11, 12, 13
Notes:
3. All outputs loaded as per maximum capacitive load table.
4. Absolute value = ((Programmed CPU Iref) x (2)) + 10 mA.
5. This parameter is measured as an average over 1-s duration, with a crystal center frequency of 14.31818 MHz
6. When Xin is driven from an external clock source.
7. This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70 but the REF clock
duty cycle will not be within data sheet specifications.
8. All outputs loaded as perTable 10.
9. Probes are placed on the pins and measurements are acquired at 1.5V for 3.3V signals (see test and measurement set-up section of this data sheet).
10.Measured between 0.2Vdd and 0.7Vdd.
11. This measurement is applicable with Spread ON or Spread OFF.
12.Measured at crossing point (Vx) or where subtraction of CLK-CLK# crosses 0 volts Measured from Vol = 0.175V to Voh = 0.525V.
13.Test load is Rta = 33.2 ohms, Rd = 49.9 ohms.
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Tskew Any CPU to CPU
Clock Skew
100 100 100 100 ps 8, 11, 12
Tccj CPU Cycle to Cycle
Jitter
150 150 150 150 ps 11, 12, 13
Tr/Tf CPUT and CPUC
Rise and Fall Times
175 700 175 700 175 700 175 700 ps 11, Notes:,
16
Rise/Fall Matching 20% 20% 20% 20% Notes:, 15,
13
DeltaTr Rise Time Variation 125 125 125 125 ps Notes:, 13
DeltaTf Fall Time Variation 125 125 125 125 ps Notes:, 13
Vcross Crossing Point
Voltage at 0.7V
Swing
280 430 280 430 280 430 280 430 mV 11, 13
CPU at 1.0V Timing
Tdc CPUT and CPUC
Duty Cycle
45 55 45 55 45 55 45 55 % 11, 12
Tperiod CPUT and CPUC
Period
14.85 15.3 9.85 10.2 7.35 7.65 4.85 5.1 nS 11, 12
Tskew Any CPU to Any
CPU Clock Skew
100 100 100 100 pS 8, 11, 12
Tccj CPU Cycle to Cycle
Jitter
150 150 150 150 pS 8, 12
Differential
Tr/Tf
CPUT and CPUC
Rise and Fall Times
175 467 175 467 175 467 175 467 ps 11, 16
SE-
DeltaSlew
Absolute Single-
ended Rise/Fall
Waveform
Symmetry
325 325 325 325 ps 17, 18
Vcross Cross Point at 1.0V
swing
510 760 510 760 510 760 510 760 mV 18
3V66
Tdc 3V66 Duty Cycle4555455545554555%8, 9
Tperiod 3V66 Period 15.0 15.3 15.0 15.3 15.0 15.3 15.0 15.3 ns 5, 8, 9
Thigh 3V66 High Time 4.95 4.95 4.95 4.95 ns 19
Tlow 3V66 Low Time 4.55 4.55 4.55 4.55 ns 20
Tr / Tf 3V66 Rise and Fall
Times
0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 ns 21
Notes:
14.Measured from Vol = 0.175V to Voh = 0.525V.
15.Determined as a fraction of 2*(Trise – Tfall)/ (Trise + Tfall).
16.Measurement taken from differential waveform, from –0.35V to +0.35V.
17. Measurements taken from common mode waveforms, measure rise/fall time from 0.41 to 0.86V. Rise/fall time matching is defined as “the instantaneous difference
between maximum clk rise (fall) and minimum clk# fall (rise) time or minimum clk rise (fall) and maximum clk# fall (rise) time”. This parameter is designed form
waveform symmetry.
18.Measured in absolute voltage, i.e. single-ended measurement.
19.THIGH is measured at 2.4V for non host outputs.
20.TLOW is measured at 0.4V for all outputs.
21.Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals (see test and measurement set-up section of this data
sheet).
AC Parameters (V
DD
= V
DDA
= 3.3V ±5%) (continued)
Parameter Description
66 MHz 100 MHz 133 MHz 200 MHz
Unit NotesMin. Max. Min. Max. Min. Max. Min. Max.

CY28346ZXC-2

Mfr. #:
Manufacturer:
Silicon Labs
Description:
Clock Synthesizer / Jitter Cleaner NB Clk Intel Brkdale 830M & 845 chipsets
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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