IDT
®
Fifteen Output Differential Buffer w/2 input mux for PCIe Gen1/2/3 1679C—10/25/16
9EX21531
Fifteen Output Differential Buffer w/2 input mux for PCIe Gen1/2/3
13
SMBusTable: Output, and PLL BW Control Register
Pin # Name Control Function T
pe 0 1 Default
Bit 7
RW Latch
Bit 6
RW Latch
Bit 5
1
Bit 4
DIF_14 Output Control RW Hi-Z Enable 1
Bit 3
0
Bit 2
1
Bit 1
0
Bit 0
1
SMBusTable: Output Control Register
Pin # Name Control Function T
pe 0 1 Default
Bit 7
1
Bit 6
DIF_6 Output Control RW Hi-Z Enable 1
Bit 5
DIF_5 Output Control RW Hi-Z Enable 1
Bit 4
DIF_4 Output Control RW Hi-Z Enable 1
Bit 3
DIF_3 Output Control RW Hi-Z Enable 1
Bit 2
DIF_2 Output Control RW Hi-Z Enable 1
Bit 1
DIF_1 Output Control RW Hi-Z Enable 1
Bit 0
DIF_0 Output Control RW Hi-Z Enable 1
SMBusTable: Output Control Register
Pin # Name Control Function Type 0 1 Default
Bit 7
DIF_13 Output Control RW Hi-Z Enable 1
Bit 6
1
Bit 5
DIF_12 Output Control RW Hi-Z Enable 1
Bit 4
DIF_11 Output Control RW Hi-Z Enable 1
Bit 3
DIF_10 Output Control RW Hi-Z Enable 1
Bit 2
DIF_9 Output Control RW Hi-Z Enable 1
Bit 1
DIF_8 Output Control RW Hi-Z Enable 1
Bit 0
DIF_7 Output Control RW Hi-Z Enable 1
SMBusTable: Output Enable Readback Register
Pin # Name Control Function T
pe 0 1 Default
Bit 7
OE10# Input Pin Readback
R
Pin Low Pin Hi X
Bit 6
OE9# Input Pin Readback
R
Pin Low Pin Hi X
Bit 5
OE8# Input Pin Readback
R
Pin Low Pin Hi X
Bit 4
OE7# Input Pin Readback
R
Pin Low Pin Hi X
Bit 3
1
Bit 2
OE6# Input Pin Readback
R
Pin Low Pin Hi X
Bit 1
OE5# Input Pin Readback
R
Pin Low Pin Hi X
Bit 0
OE_01234# Input Pin Readback
R
Pin Low Pin Hi X
B
te 0
B
te 2
B
te 1
PLL_BW# adjust
BYPASS# test mode / PLL
54
30
46
43
50
1
4
B
te 3
63
00 = Low BW (1MHz)
10 = Bypass
11 = High BW (3MHz)
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
