IDT
®
Fifteen Output Differential Buffer w/2 input mux for PCIe Gen1/2/3 1679C—10/25/16
9EX21531
Fifteen Output Differential Buffer w/2 input mux for PCIe Gen1/2/3
4
Pin Description (Continued)
33 DIF_1 OUT 0.7V differential true clock output
34 DIF_1# OUT 0.7V differential complement clock output
35 DIF_2 OUT 0.7V differential true clock output
36 DIF_2# OUT 0.7V differential complement clock output
37 VDD PWR Power supply, nominal 3.3V
38 GND PWR Ground pin.
39 DIF_3 OUT 0.7V differential true clock output
40 DIF_3# OUT 0.7V differential complement clock output
41 DIF_4 OUT 0.7V differential true clock output
42 DIF_4# OUT 0.7V differential complement clock output
43 OE5# IN
Active low input for enabling DIF pair 5.
1 = tri-state outputs, 0 = enable outputs
44 DIF_5 OUT 0.7V differential true clock output
45 DIF_5# OUT 0.7V differential complement clock output
46 OE6# IN
Active low input for enabling DIF pair 6.
1 = tri-state outputs, 0 = enable outputs
47 DIF_6 OUT 0.7V differential true clock output
48 DIF_6# OUT 0.7V differential complement clock output
49 VDD PWR Power supply, nominal 3.3V
50 OE7# IN
Active low input for enabling DIF pair 7.
1 = tri-state outputs, 0 = enable outputs
51 DIF_7 OUT 0.7V differential true clock output
52 DIF_7# OUT 0.7V differential complement clock output
53 VDD PWR Power supply, nominal 3.3V
54 HIBW_BYPM_LOBW# IN
Trilevel input to select High BW, Bypass Mode or Low BW.
0 = Low BW Mode, Mid= Bypass Mode, 1 = High Bandwidth
55 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant
56 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant
57 SMB_A1 IN SMBus address bit 1
58 SMB_A0 IN SMBus address bit 0 (LSB)
59 SEL_A_B# IN
Input to select differential input clock A or differential input clock B.
0 = Input B selected, 1 = Input A selected.
60 CKPWRGD/PD# IN Notifies the clock to sample latched inputs on the rising edge, and to power down on the falling edge.
61 DIF_8 OUT 0.7V differential true clock output
62 DIF_8# OUT 0.7V differential complement clock output
63 OE8# IN
Active low input for enabling DIF pair 8.
1 = tri-state outputs, 0 = enable outputs
64 VDD PWR Power supply, nominal 3.3V
IDT
®
Fifteen Output Differential Buffer w/2 input mux for PCIe Gen1/2/3 1679C—10/25/16
9EX21531
Fifteen Output Differential Buffer w/2 input mux for PCIe Gen1/2/3
5
Electrical Characteristics - Absolute Maximum Ratings
PARAMETER SYMBOL CONDITIONS
MIN TYP MAX
UNITS NOTES
3.3V Core Supply Voltage VDDA 4.6 V 1,2
3.3V Logic Supply Voltage VDD 4.6 V 1,2
Input Low Voltage V
IL
GND-0.5 V 1
Input High Voltage V
IH
Except for SMBus interface V
D
D
+0.5V V 1
Input High Voltage V
IHSMB
SMBus clock and data pins 5.5V V 1
Storage Temperature Ts -65 150
°
C
1
Junction Temperature Tj 125 °C 1
Input ESD protection
ESD prot Human Body Model 2000 V 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor guaranteed.
Electrical Characteristics - Input/Supply/Common Parameters
TA = T
COM
or T
IND
;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Ambient Operating
Temperature
T
COM
Commmercial range 0 70 °C 1
Input High Voltage V
IH
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
2V
DD
+ 0.3 V 1,6
Input Low Voltage V
IL
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
GND
- 0.3 0.8 V 1,6
I
IN
Single-ended inputs, V
IN
= GND, V
IN
= VDD -5 5 uA 1
I
INP
Single-ended inputs
V
IN
= 0 V; Inputs with internal pull-up resistors
V
IN
= VDD; Inputs with internal pull-down resistors
-200 200 uA 1
F
ib
yp
V
D
D
= 3.3 V, Bypass mode 33 167 MHz 2
F
i
ll
V
D
D
= 3.3 V, 100MHz PLL mode 80 100 110 MHz 2
Pin Inductance L
p
in
7nH1
C
IN
Logic Inputs, except DIF_IN 1.5 5 pF 1
C
INDIF_IN
DIF_IN differential clock inputs 1.5 2.7 pF 1,4
C
OUT
Output pin capacitance 6 pF 1
Clk Stabilization T
STAB
From V
DD
Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
0.50 1 ms 1,2
Input SS Modulation
Frequency
f
MODIN
Allowable Frequency
(Triangular Modulation)
30 33 kHz 1
OE# Latency t
LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
412cycles1,3
Tdrive_PD# t
DRVPD
DIF output enable after
PD# de-assertion
300 us 1,3
Tfall t
F
Fall time of control inputs 5 ns 1,2
Trise t
R
Rise time of control inputs 5 ns 1,2
SMBus Input Low Voltage V
ILSMB
0.8 V 1
SMBus Input High Voltage V
IHSMB
2.1 V
DDSMB
V1
SMBus Output Low Voltage V
OLSMB
@ I
PULLUP
0.4 V 1
SMBus Sink Current I
PULLUP
@ V
OL
4mA1
Nominal Bus Voltage V
DDSMB
3V to 5V +/- 10% 2.7 5.5 V 1
SCLK/SDATA Rise Time t
RSMB
(Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA Fall Time t
FSMB
(Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
SMBus Operating
Frequency
f
MAXSMB
Maximum SMBus operating frequency 100 kHz 1,5
1
Guaranteed by design and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swing.
6
See the functionalit
y
tables for the thresholds for the tri-level and low threshold in
p
uts.
Input Frequency
5
The differential in
p
ut clock must be runnin
g
for the SMBus to be active
Input Current
3
Time from deassertion until out
p
uts are >200 mV
4
DIF_IN input
Capacitance
IDT
®
Fifteen Output Differential Buffer w/2 input mux for PCIe Gen1/2/3 1679C—10/25/16
9EX21531
Fifteen Output Differential Buffer w/2 input mux for PCIe Gen1/2/3
6
Electrical Characteristics - Clock Input Parameters
TA = T
COM;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input High Voltage - DIF_IN V
I HDI F
Differential inputs
(single-ended measurement)
600 800 1150 mV 1
Input Low Voltage - DIF_IN V
ILDIF
Differential inputs
(single-ended measurement)
V
SS
- 300 0 300 mV 1
Input Common Mode
Voltage - DIF_IN
V
COM
Common Mode Input Voltage 300 1000 mV 1
Input Amplitude - DIF_IN V
SWING
Peak to Peak value 300 1450 mV 1
Input Slew Rate - DIF_IN dv/dt Measured differentially 0.4 8 V/ns 1,2
Input Leakage Current I
IN
V
IN
= V
DD
,
V
IN
=
GND -5 5 uA 1
Input Duty Cycle d
tin
Measurement from differential wavefrom 45 55 % 1
Input Jitter - Cycle to Cycle J
DIFIn
Differential Measurement 0 125 ps 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Slew rate measured through +/-75mV window centered around differential zero
Electrical Characteristics - DIF 0.7V Current Mode Differential Outputs
T
A
= T
COM;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Slew rate Trf Scope avera
g
in
g
on 1 4
V/ns
1, 2, 3
Slew rate matchin
g
Trf
Slew rate matchin
g
, Sco
p
e avera
g
in
g
on 20
%
1, 2, 4
Voltage High VHigh 660 850 1
Voltage Low VLow -150 150 1
Max Volta
g
eVmax 1150 1
Min Volta
g
eVmin -300 1
Vswin
g
Vswin
g
Scope avera
g
in
g
off 300 mV 1, 2
Crossin
g
Volta
g
e
(
abs
)
Vcross_abs Sco
p
e avera
g
in
g
off 250 550 mV 1, 5
Crossing Voltage (var) -Vcross Scope averaging off 140 mV 1, 6
2
Measured from differential waveform
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross absolute)
allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.
mV
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope averaging
on)
Measurement on single ended signal using absolute
value. (Scope averaging off)
mV
1
Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xR
R
). For R
R
= 475
(1%), I
REF
= 2.32mA. I
OH
=
6 x I
REF
and V
OH
= 0.7V @ Z
O
=50
(100 differential impedance).
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate of Clock / falling edge rate of Clock#. It is measured in a +/-75mV window centered on the average
cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope uses
for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e.
Clock rising and Clock# falling).
Electrical Characteristics - Current Consumption
T
A
= 0 - 70°C; Su
pp
l
y
Volta
g
e V
DD/
V
DDA
= 3.3 V +/-5%,
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
I
DD3.3OP
VDD rail. All outputs active @100MHz, C
L
=
Full load;
300 350 mA 1
I
DD3.3AOP
VDDA rail. All outputs active @100MHz, C
L
=
Full load;
30 40 mA 1
I
DD3. 3PDZ
VDD Rail, All differential pairs tri-stated 12 15 mA 1
I
DD3.3APDZ
VDDA Rail, All differential pairs tri-stated 13 18 mA 1
1
Guaranteed b
y
desi
g
n and characterization, not 100% tested in
p
roduction.
Operating Supply Current
Powerdown Current

9EX21531AKLFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products PCIE BUFFER - GEN3 15 OUTPUTS w/2:1 INP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet