IDT
®
Fifteen Output Differential Buffer w/2 input mux for PCIe Gen1/2/3 1679C—10/25/16
9EX21531
Fifteen Output Differential Buffer w/2 input mux for PCIe Gen1/2/3
7
Electrical Characteristics - Skew and Differential Jitter Parameters
T
A
= 0 - 70°C; Supply Voltage V
DD/
V
DDA
= 3.3 V +/-5%,
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
CLK_IN, DIF[x:0] t
SPO_PLL
Input-to-Output Skew in PLL mode
nominal value @ 25°C, 3.3V
900 1000 1125 ps 1,2,4,5,8
CLK_IN, DIF[x:0] t
PD_BYP
Input-to-Output Skew in Bypass mode
nominal value @ 25°C, 3.3V
4000 4700 5200 ns 1,2,3,5,8
CLK_IN, DIF[x:0] t
DSPO_PLL
Input-to-Output Skew Varation in PLL mode
across volta
e and tem
erature
|250| |350| ps 1,2,3,5,8
CLK_IN, DIF[x:0] t
DSPO_BYP
Input-to-Output Skew Varation in Bypass mode
across voltage and temperature
|800| |900| ps 1,2,3,5,8
CLK_IN, DIF[x:0] t
DTE
Random Differential Tracking error beween two
9EX devices in Hi BW Mode
25
ps
rms
1,2,3,5,8
CLK_IN, DIF[x:0] t
DSSTE
Random Differential Spread Spectrum Trackin
error beween two 9EX devices in Hi BW Mode
20 75 ps 1,2,3,5,8
DIF{x:0] t
SKEW_ALL
Output-to-Output Skew across all outputs
(Common to Bypass and PLL mode)
75 150 ps 1,2,3,8
PLL Jitter Peaking j
eak-hibw
LOBW#_BYPASS_HIBW = 1 0 2.5 3 dB 7,8
PLL Jitter Peaking j
eak-lobw
LOBW#_BYPASS_HIBW = 0 0 2 2.5 dB 7,8
PLL Bandwidth pll
HIBW
LOBW#_BYPASS_HIBW = 1 2 3 4 MHz 8,9
PLL Bandwidth pll
LOB
LOBW#_BYPASS_HIBW = 0 0.7 1 1.4 MHz 8,9
Duty Cycle t
DC
Measured differentially, PLL Mode 45 50 55 % 1
Duty Cycle Distortion t
DCD
Measured differentially, Bypass Mode
@100MHz
-2 0 2 % 1,10
PLL mode 30 50
s1,11
Additive Jitter in Bypass Mode 20 50 ps 1,11
Notes for preceding table:
6.
t is the
eriod of the in
ut clock
7
Measured as maximum
ass band
ain. At fre
uencies within the loo
BW, hi
hest
oint of ma
nification is called PLL
itter
eakin
.
8.
Guaranteed b
desi
n and characterization, not 100% tested in
roduction.
9
Measured at 3 db down or half
ower
oint.
10
Dut
c
cle distortion is the difference in dut
c
cle between the out
ut and the in
ut clock when the device is o
erated in b
ass mod
11
Measured from differential waveform
2
Measured from differential cross-
oint to differential cross-
oint.
3
All B
ass Mode In
ut-to-Out
ut s
ecs refer to the timin
between an in
ut ed
e and the s
ecific out
ut ed
e created b
it.
4
This
arameter is deterministic for a
iven device
5
Measured with sco
e avera
in
on to find mean value.
Jitter, Cycle to cycle t
jcyc-cyc
1
Measured into fixed 2
F load ca
. In
ut to out
ut skew is measured at the first out
ut ed
e followin
the corres
ondin
in
ut.
