74LVC594A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 21 October 2013 9 of 20
NXP Semiconductors
74LVC594A
8-bit shift register with output register
[1] Typical values are measured at T
amb
=25C and V
CC
= 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2] t
pd
is the same as t
PLH
and t
PHL
.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of outputs.
t
h
hold time DS to SHCP; see Figure 9
V
CC
= 1.65 V to 1.95 V 1.5 0.2 - 2.0 - ns
V
CC
= 2.3 V to 2.7 V 1.5 0.1 - 2.0 - ns
V
CC
= 2.7 V 1.5 0.1 - 2.0 - ns
V
CC
= 3.0 V to 3.6 V 1.0 0.2 - 1.5 - ns
t
rec
recovery time SHR to SHCP, STR to STCP;
see Figure 11
and Figure 12
V
CC
= 1.65 V to 1.95 V 5.0 2.7 - 5.5 - ns
V
CC
= 2.3 V to 2.7 V 4.0 1.5 - 4.5 - ns
V
CC
= 2.7 V 2.0 1.0 - 2.5 - ns
V
CC
= 3.0 V to 3.6 V 2.0 1.0 - 2.5 - ns
f
max
maximum
frequency
SHCP or STCP; see Figure 7
and Figure 8
V
CC
= 1.65 V to 1.95 V 80 130 - 70 - MHz
V
CC
= 2.3 V to 2.7 V 100 140 - 90 - MHz
V
CC
= 2.7 V 110 150 - 100 - MHz
V
CC
= 3.0 V to 3.6 V 130 180 - 115 - MHz
t
sk(o)
output skew time V
CC
= 3.0 V to 3.6 V
[3]
--1.0- 1.5ns
C
PD
power dissipation
capacitance
V
I
= GND to V
CC
[4]
V
CC
= 1.65 V to 1.95 V - 50 - - - pF
V
CC
= 2.3 V to 2.7 V - 45 - - - pF
V
CC
= 3.0 V to 3.6 V - 44 - - - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13.
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
74LVC594A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 21 October 2013 10 of 20
NXP Semiconductors
74LVC594A
8-bit shift register with output register
12. Waveforms
Measurement points are given in Table 8.
V
OL
and V
OH
are typical output voltage drops that occur with the output load.
Fig 7. The shift clock (SHCP) to serial data output (Q7S) propagation delays, the shift clock pulse width and
maximum shift clock frequency
mna557
SHCP
input
Q
7S output
t
PLH
t
PHL
t
W
1/f
max
V
M
V
OH
V
I
GND
V
OL
V
M
Measurement points are given in Table 8.
V
OL
and V
OH
are typical output voltage drops that occur with the output load.
Fig 8. The storage clock (STCP) to parallel data output (Qn) propagation delays, the storage clock pulse width
and the shift clock to storage clock set-up time
mna558
STCP
input
Q
n output
t
PLH
t
PHL
t
W
t
su
1/f
max
V
M
V
OH
V
I
GND
V
OL
V
M
SHCP
input
V
I
GND
V
M
74LVC594A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 21 October 2013 11 of 20
NXP Semiconductors
74LVC594A
8-bit shift register with output register
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
V
OL
and V
OH
are typical output voltage drops that occur with the output load.
Fig 9. The data set-up and hold times for the serial data input (DS)
mna560
GND
GND
t
h
t
su
t
h
t
su
V
M
V
M
V
M
V
I
V
OH
V
OL
V
I
Q7S output
SH
CP input
D
S input
Measurement points are given in Table 8.
V
OL
and V
OH
are typical output voltage drops that occur with the output load.
Fig 10. The shift reset (SHR) to storage clock (STCP) set-up times
PEF
9
0
W
VX
9
0
9
0
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6+5LQSXW

74LVC594APW,118

Mfr. #:
Manufacturer:
Nexperia
Description:
Counter Shift Registers 3.3V SHIFT REG WITH
Lifecycle:
New from this manufacturer.
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