74LVC594A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 21 October 2013 3 of 20
NXP Semiconductors
74LVC594A
8-bit shift register with output register
Fig 3. Logic diagram
PEF
4 4 4 4 4 4 4
'6
6+&3
6+5
67&3
675
'
4
&3
))6+
5
67$*(
'
4
&3
))67
5
67$*(672
'4
4
'4
&3
))6+
5
67$*(
'
4
&3
))67
5
46
Fig 4. Timing diagram
PEF
46
4
675
6+5
67&3
'6
6+&3
4
4
4
74LVC594A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 21 October 2013 4 of 20
NXP Semiconductors
74LVC594A
8-bit shift register with output register
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 5. Pin configuration SO16 and TSSOP16 Fig 6. Pin configuration DHVQFN16
001aag288
74LVC594A
Q7 SHR
Q6 SHCP
Q5 STCP
Q4 STR
Q3 DS
Q2 Q0
GND
Q7S
Q1
V
CC
Transparent top view
7 10
6 11
5 12
4
13
3 14
2 15
8
9
1
16
terminal 1
index area
Table 2. Pin description
Symbol Pin Description
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 15, 1, 2, 3, 4, 5, 6, 7 parallel data output
GND 8 ground (0 V)
Q7S 9 serial data output
SHR
10 shift register reset (active LOW)
SHCP 11 shift register clock input
STCP 12 storage register clock input
STR
13 storage register reset (active LOW)
DS 14 serial data input
V
CC
16 supply voltage
74LVC594A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 21 October 2013 5 of 20
NXP Semiconductors
74LVC594A
8-bit shift register with output register
7. Functional description
[1] H = HIGH voltage state;
L = LOW voltage state;
= LOW-to-HIGH transition;
X = don’t care;
NC = no change;
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO16 packages: above 70 C the value of P
tot
derates linearly with 8 mW/K.
For TSSOP16 packages: above 60 C the value of P
tot
derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 C the value of P
tot
derates linearly with 4.5 mW/K.
Table 3. Function table
[1]
Input Output Function
SHCP STCP SHR STR DS Q7S Qn
XXLXXLNCa LOW-state on SHR
only affects the shift register
X X X L X NC L a LOW-state on STR
only affects the storage register
X L H X L L empty shift register loaded into storage register
X H X H Q6S NC logic HIGH level shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S).
X H H X NC QnS contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages
H H X Q6S QnS contents of shift register shifted through; previous contents of the
shift register is transferred to the storage register and the parallel
output stages
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +6.5 V
I
IK
input clamping current V
I
<0 V 50 - mA
V
I
input voltage
[1]
0.5 +6.5 V
I
OK
output clamping current V
O
>V
CC
or V
O
<0 V - 50 mA
V
O
output voltage 3-state
[1]
0.5 6.5 V
output HIGH or LOW state
[1]
0.5 V
CC
+0.5 V
I
O
output current V
O
=0 VtoV
CC
- 50 mA
I
CC
supply current - 100 mA
I
GND
ground current 100 - mA
T
stg
storage temperature 65 +150 C
P
tot
total power dissipation T
amb
= 40 C to +125 C
[2]
-500 mW

74LVC594APW,118

Mfr. #:
Manufacturer:
Nexperia
Description:
Counter Shift Registers 3.3V SHIFT REG WITH
Lifecycle:
New from this manufacturer.
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