LTC3626
22
3626fa
For more information www.linear.com/LTC3626
applicaTions inForMaTion
From the previous section, I
GATECHG
is approximately 5mA
when f = 2MHz, and the spec table lists the typical I
Q
to be
approximately 1mA. Therefore, the total power dissipation
due to resistive losses and LDO losses is:
P
D
= I
OUT
2
• R
SW
+ V
IN
• (I
GATECHG
+ I
Q
)
P
D
= (2.5A)
2
• (0.092Ω) + 12V • 5mA = 635mW
The QFN 3mm × 4mm package junction-to-ambient thermal
resistance, θ
JA
, is approximately 47°C/W. Therefore, the
junction temperature of the regulator operating in a 70°C
ambient temperature is approximately:
T
J
= 0.63W • 47°C/W + 70°C = 100°C
which is below the maximum junction temperature of
125°C.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3626.
1. Does the capacitor C
IN
connect to PV
IN
and PGND as
close to the pins as possible? These capacitors provide
the AC current to the internal power MOSFETs. The (–)
plate of C
IN
should be closely connected to PGND and
the (–) plate of C
OUT
.
2. The output capacitor, C
OUT
, and inductor L1 should
be closely connected to minimize loss. The (–) plate
of C
OUT
should be closely connected to PGND and the
(–) plate of C
IN
.
3. The resistive divider, R1 and R2, must be connected
between the (+) plate of C
OUT
and a ground line termi-
nated near SGND. The feedback signal, V
FB
, should be
routed away from noisy components and traces such as
the SW and BOOST lines, and its trace length should be
minimized. In addition, RT, compensation components,
and current and temperature monitor/limit components
should be terminated to SGND.
4. Keep sensitive components away from the SW and
BOOST pins. The R
RT
resistor, the feedback resistors,
the compensation components, the current monitor
components, and the INTV
CC
bypass capacitor should
all be routed away from the SW trace and the inductor.
5. A ground plane is preferred, but if not available the
signal and power grounds should be segregated with
both connecting to a common, low noise reference
point. The point at which the ground terminals of the
V
IN
and V
OUT
bypass capacitors are connected makes a
good, low noise reference point. The connection to the
PGND pin should be made with a minimal resistance
trace from the reference point.
6. Flood all unused areas on all layers with copper in order
to reduce the temperature rise of power components.
These copper areas should be connected to the exposed
backside connection of the IC.
Design Example
As a design example, consider using the LTC3626 in an
application with the following specifications:
V
IN
= 12V, V
OUT
= 1.8V, I
OUT(MAX)
= 2.5A, I
OUT(MIN)
=
50mA
Further, the ability to continuously monitor the average
output current (I
OUT
) and the internal temperature is de-
sired. Finally, an average I
OUT
limit of 2.5A and an internal
temperature limit of approximately 125°C are desired.
Because efficiency is important at both high and low load
currents, Burst Mode operation and 1MHz operation is
chosen.
First, the correct R
RT
resistor value for 1MHz switching
frequency must be chosen. Based on the equation in the
Applications Information section, R
RT
is calculated to be
320k. A standard 324k resistor is selected for R
RT
.
