MAX3580ETJ+ Datasheet MAX3580ETJ+, MAX3580ETJ+T | P16-P18

MAX3580

Direct-Conversion TV Tuner

16 ______________________________________________________________________________________

To Read Back Fuses

IMPORTANT NOTICE: When reading other addresses

than 8’h00 (the system trim bits), it is possible that the

data going to the bias cells will be disturbed due to the

architecture of the fuse bank. This means the bias cur-

rent could change while reading back fuse data.

1) Write 8’hXX to TFA. XX is the address of the fuse col-

umn you want to read.

2) Read 8’hXX from TFR. TFR is the Tracking Filter

Read Register.

3) Repeat steps 1 and 2 for other addresses.

2-Wire Serial Interface

The MAX3580 uses a 2-wire I

C-compatible serial inter-

face consisting of a serial-data line (SDA) and a serial-

clock line (SCL). The serial interface allows

communication between the MAX3580 and the master

at clock frequencies up to 400kHz. The master initiates

a data transfer on the bus and generates the SCL sig-

nal to permit data transfer. The MAX3580 behaves as

slave devices that transfer and receive data to and from

the master. Pull SDA and SCL high with external pullup

resistors (1kΩ or greater) for proper bus operation.

One bit is transferred during each SCL clock cycle. A

minimum of nine clock cycles are required to transfer a

byte in or out of the MAX3580 (8 bits and an ACK/NACK).

The data on SDA must remain stable during the high peri-

od of the SCL clock pulse. Changes in SDA while SCL is

high and stable are considered control signals (see the

START and STOP Conditions

section). Both SDA and

SCL remain high when the bus is not busy.

START and STOP Conditions

The master initiates a transmission with a START condi-

tion (S), which is a high-to-low transition on SDA while

SCL is high. The master terminates a transmission with

a STOP condition (P), which is a low-to-high transition

on SDA while SCL is high.

Acknowledge and Not-Acknowledge Conditions

Data transfers are framed with an acknowledge bit

(ACK) or a not-acknowledge bit (NACK). Both the mas-

ter and the MAX3580 (slave) generate acknowledge

bits. To generate an acknowledge, the receiving device

must pull SDA low before the rising edge of the

acknowledge-related clock pulse (ninth pulse) and

keep it low during the high period of the clock pulse.

To generate a not-acknowledge condition, the receiver

allows SDA to be pulled high before the rising edge of

the acknowledge-related clock pulse, and leaves SDA

high during the high period of the clock pulse.

Monitoring the acknowledge bits allows for detection of

unsuccessful data transfers. An unsuccessful data

transfer happens if a receiving device is busy or if a

system fault has occurred. In the event of an unsuc-

cessful data transfer, the bus master must reattempt

communication at a later time.

Slave Address

The MAX3580 has a 7-bit slave address that must be

sent to the device following a START condition to initi-

ate communication. The slave address is determined

by the state of the ADDR2 pin and is equal to

11000[ADDR2]0 (see Table 4). The eighth bit (R/W) fol-

lowing the 7-bit address determines whether a read or

write operation will occur.

The MAX3580 continuously awaits a START condition

followed by its slave address. When the device recog-

nizes its slave address, it acknowledges by pulling the

SDA line low for one clock period; it is ready to accept

or send data depending on the R/W bit (Figure 2).

Table 4. Address Configuration

ADDRESS (WRITE/READ) ADDR2

C0/C1

HEX

C4/C5

HEX

SCL

SDA

123456789

S11000 0R/ WACK

SLAVE ADDRESS

ADDR2

Figure 2. MAX3580 Slave Address Byte

MAX3580

Direct-Conversion TV Tuner

______________________________________________________________________________________ 17

Write Cycle

When addressed with a write command, the MAX3580

allows the master to write to a single register or to multi-

ple successive registers.

A write cycle begins with the bus master issuing a

START condition followed by the seven slave address

bits and a write bit (R/W = 0). The MAX3580 issues an

ACK if the slave address byte is successfully received.

The bus master must then send to the slave the

address of the first register it wishes to write to. If the

slave acknowledges the address, the master can then

write one byte to the register at the specified address.

Data is written beginning with the most significant bit.

The MAX3580 again issues an ACK if the data is suc-

cessfully written to the register. The master can contin-

ue to write data to the successive internal registers with

the MAX3580 acknowledging each successful transfer,

or it can terminate transmission by issuing a STOP con-

dition. The write cycle does not terminate until the mas-

ter issues a STOP condition.

Figure 3 illustrates an example in which Registers 0

through 2 are written with 0x0E, 0xD8, and 0xE1,

respectively.

Read Cycle

When addressed with a read command, the MAX3580

allows the master to read back a single register or mul-

tiple successive registers.

A read cycle begins with the bus master issuing a

START condition followed by the 7 slave address bits

and a write bit (R/W = 0). The MAX3580 issues an ACK if

the slave address byte is successfully received. The bus

master must then send the address of the first register it

wishes to read. The slave acknowledges the address.

Then a START condition is issued by the master, fol-

lowed by the 7 slave address bits and a read bit (R/W =

1). The MAX3580 issues an ACK if the slave address

byte is successfully received. The MAX3580 starts send-

ing data MSB first with each SCL clock cycle. At the 9th

clock cycle, the master can issue an ACK, and continue

to read successive registers, or the master terminate the

transmission by issuing a NACK. The read cycle does

not terminate until the master issues a STOP condition.

Figure 4 illustrates an example in which Registers 0

through 2 are read back.

START

WRITE DEVICE

ADDRESS

R/ W

1100000

WRITE REGISTER

ADDRESS

0x000

ACK

WRITE DATA TO

0x0E

ACK

WRITE DATA TO

0xD8

ACK

WRITE DATA TO

0xE1

ACK

STOP

Figure 3. Example: Write Registers 0 through 2 with 0x0E, 0xD8 and 0xE1, respectively.

DEVICE

ADDRESS

DEVICE

ADDRESS

REG 00

DATA

REG 01

DATA

REG 02

DATA

ADDRESS

R/ W

11000000 00000000 11000000 xxxxxxxx xxxxxxxx xxxxxxxx01

R/ W

Figure 4. Example: Receive data from read registers.

MAX3580

Direct-Conversion TV Tuner

18 ______________________________________________________________________________________

Applications Information

Band Selection

The MAX3580 is designed to be suitable for operation

in the 170MHz to 230MHz VHF-III band and in the

470MHz to 878MHz UHF band.

RF Inputs

A switch selects either RFIN or RFIN2 as the input to the

single-ended broadband matched LNA. This switch is

programmed through the RFS bit (bit 5) of register 0x05.

The LNA provides a continuous gain control range of

typically 50dB before the signal is downconverted.

For optimal matching above 600MHz, add a 5nH to

6nH inductor in series with a capacitor at either of the

RF input. Application Note:

Front End Diplexer Filter for

MAX3580

is available, detailing the implementation of a

UHF and VHF simple diplexer. This simple diplexer

improves strong-signal-handling capabilities of the

MAX3580.

DC-Offset Cancellation

The MAX3580 features an on-chip fast-settling, DC-off-

set cancellation circuitry that requires no off-chip com-

ponents. Note that the offset correction circuit is not

enabled when the device is powered up. To enable the

offset correction circuit, program the DC-Offset Control

When active, the offset correction circuit creates a high-

pass characteristic in the signal path with a typical cor-

ner frequency of 200Hz, and the residual DC offset can

be as high as ±70mV.

Gain Control

The MAX3580 features two VGA circuits that can be

used to achieve the optimum SNR. The two circuits can

be driven independently by the baseband controller,

which allows balancing the gain based on SNR measure-

ments in the digital demodulator. If only one gain control

voltage can be provided by the digital demodulator, see

Figure 1. See the

Baseband Power Detector

section. In

this operation mode, the baseband gain is set by an

amplitude detector in the digital demodulator.

Baseband Power Detector

Maxim recommends disabling this feature. See expla-

nation in the

Shutdown Control (Register Address 0x08)

section and Table 2 (address 0x08, bit D5). For single-

loop AGC control, see Figure 1.

Synthesizer Loop Filters

A second-order lowpass loop filter is used to connect

the PLL to the RF local oscillator. A loop filter bandwidth

of 30kHz is optimal for fractional PLL spurs and integrat-

ed LO phase noise. Refer to the EV kit data sheet for the

recommended loop-filter component values.

Crystal-Oscillator Interface

The MAX3580 reference oscillator circuitry can be used

either as a high-impedance reference input driven by

an external source, or be configured as a crystal oscil-

lator. In the latter case, the resulting frequency can be

used to drive the digital demodulator chip through the

buffered reference output of the MAX3580. When using

an external reference oscillator, drive the XB input

through an AC-coupling capacitor with amplitude of

approximately 1.5V

P-P

, and leave XE unconnected.

Note that the phase noise of the external reference

needs to exceed -140dBc/Hz at offsets of 1kHz to

100kHz. When connecting directly to a crystal, see the

Typical Application Circuit

for the required topology.

For particular capacitor values, possible changes to

accommodate for different crystal frequencies, crystal

load-capacitance requirements, and crystal power-dis-

sipation requirements, refer to the EV kit data sheet.

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MAX3580ETJ+

Mfr. #:

Buy MAX3580ETJ+

Manufacturer:

Maxim Integrated

Description:

Tuners Direct Conversion TV Tuner

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New from this manufacturer.

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MAX3580ETJ+

MAX3580ETJ+

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