LTC2960
10
2960fa
For more information www.linear.com/LTC2960
applicaTions inForMaTion
pull-up circuitry. A 100k resistor from output to ground is
satisfactory for most applications. When the status outputs
are high, power is dissipated in the pull-down resistors.
If V
CC
falls below the falling UVLO threshold, the outputs
are pulled to ground. The outputs are guaranteed to stay
low for V
CC
≥ 1.2V regardless of the output logic configura-
tion. When V
CC
< 1.2V, the active pull-up output behaves
similarly to an open-drain output with a pull-up resistor.
and MR is a solution to this issue. The MR input can be
pulled to 36V maximum and will not affect the internal
circuitry. Input MR is often pulled down through the use
of a pushbutton switch.
SELECTING THE RESET TIMEOUT PERIOD
Use the RT input (LTC2960-1/ LTC2960-2) to select
between two fixed reset timeout periods. Connect RT to
ground for a 15ms timeout. Connect RT to V
CC
for a 200ms
timeout. The reset timeout period occurs after the ADJ
input is driven above threshold and the MR input transitions
above its logic threshold. After the reset timeout period,
the RST output is allowed to pull up to a high state as
shown in Figure 5.
The RT input
is replaced by the DV
CC
input in the LTC2960-3/LTC2960-4 options and the reset
timeout period defaults to 200ms.
0.4V
IN
+
LTC2960-3
(a). PUSH-PULL CONFIGURATION
(b). OPEN-DRAIN CONFIGURATION
DV
CC
1.6V TO 5.5V
6.3V MAX
OUT
LTC2960-3
DV
CC
OUT
+
0.4V
IN
+
+
2960 F04
Figure 4. LTC2960-3 (LTC2960-4) RST and OUT Outputs
Are Configurable as Push-Pull or Open-Drain
ADJ
15ms
200ms
2960 F05
RST, RT = GND
RST, RT = V
CC
Figure 5. Selectable Reset Timeout Period
MANUAL RESET INPUT
When ADJ is above its reset threshold and the manual
reset input (MR) is pulled low, the RST output is forced
low. RST remains low for the selected reset timeout period
after the manual reset input is released and pulled high.
The manual reset input is pulled up internally through a
1µA current source to an internal bias voltage (see Elec
-
trical Characteristics).
If external leakage currents have
the ability to pull down the manual reset input below its
logic threshold, a pull-up resistor placed between V
CC
EXTERNAL HYSTERESIS
The LTC2960 IN
+
comparator hysteresis is 20mV (V
+
HYS
),
or 5% referred to V
TH
. Certain applications require more
than the built-in native hysteresis. The application sche-
matic in
Figure 6 adds one additional resistor (R6) to a
typical
attenuator network. The procedure below is used
to determine a value for R6 to provide an increase over the
native hysteresis. In this example, it is desired to double
the native hysteresis from 300mV to 600mV and achieve
a falling threshold of 6V.
Before including R6, the rising threshold (V
R
) is 6.293V
while the falling threshold (V
F
) is 5.993V. The hysteresis
referred to V
A
is calculated from:
V
HYST VA
( )
= V
PHYS
1+
R4
R5
=20mV 15 = 300mV
LTC2960
11
2960fa
For more information www.linear.com/LTC2960
2960 F06
DV
CC
OUTIN
+
LTC2960-3
R6
6.81M
V
B
V
A
R4
681k
R5
48.7k
Figure 6. External Hysteresis
The addition of R6 allows OUT to sink or source current
to the summing junction at IN
+
. Neglecting internal switch
resistances and providing that R6 >> R5, the externally
modified hysteresis (referred to V
A
) becomes:
V
HEXT
V
HYS(VA)
+ V
B
R4
R6
Since the amount of hysteresis is to be doubled, the
second
term in the above expression needs to be about
300mV. With a logic supply, V
B
, equal to 3V, the ratio R4/
R6 should be about 0.1. Choosing R6 to be 6.81M satisfies
the design criteria.
The addition of R6 modifies the rising and falling thresholds
originally determined by R4 and R5. The modified rising
threshold becomes:
V
R
= V
TH
+ V
+
HYS
( )
1+
R4
R5
+
R4
R6
= 400mV + 20mV
( )
1+ 13.98+ 0.1
( )
= 6.3336V
It is apparent that the R4/R6 term does not affect the ris-
ing threshold
significantly resulting in a change of only
+0.645%. The falling threshold incorporating R6 is:
V
F
= V
TH
1+
R4
R5
+
R4
R6
V
TH
– V
B
V
TH
= 0.4V 1+ 13.98 0.65
( )
= 5.732V
applicaTions inForMaTion
The falling threshold can be restored to the original value
by reducing the value of R5. Under the assumption that
the addition of R6 has a negligible impact on the rising
threshold, a new R4/R5 ratio can be calculated as shown:
R4
R5
=
V
R
V
TH
+ V
+
HYS
( )
1=
6.6V
420mV
1= 14.7
1
Given the ratio of R4/R5, the closest 1% resistor value for
R5 is 46.4k. With the actual resistor values now known,
the final thresholds can be calculated by plugging the
values into the equations above for V
R
and V
F
to obtain:
V
R
= 6.626V, V
F
= 6.010V, V
HYST
= 616mV
As a result of the added current component through R6
an error term exists that is a function of the pull-up volt-
age, V
B
in Figure 6.
Operation with Supply Transients over 40V and Hot
Swapping
The circuit in Figure 7(a) allows the LTC2960 to withstand
high voltage transients. The magnitude of the voltage
transients that can be absorbed is set by the voltage rat
-
ing of RZ. A TT-IRC pulse-withstanding surface mount
1206 resistor with a nominal voltage rating of 200V is
used. The external 30V Zener diode (Z1) and the 143
current limiting resistor (RZ) protect the V
IN
supply pin
of the LTC2960. Note that there is a speed penalty which
is the time constant determined by RZ and C1, 14.3ms in
this example. If V
IN
is below 30V, there is a voltage drop
across RZ that is dependent on the quiescent current of
the LTC2960 which is nominally less than 150mV but can
be as high as 290mV if MR is pulled low. The maximum
voltage drop is determined by the maximum specified I
CC
and MR pull-up currents. For conditions where the Zener
conducts current, it can be biased in the microamp range
owing
to the low quiescent current of the LTC2960. For a
supply voltage of 150V, the Zener is biased <1mA. When
input pins are used to sense V
IN
, the input pins ADJ/IN
+
/
IN
absolute maximum rating of 3.5V must not be exceeded.
V
IN
can be a maximum of 8.75x the lowest programmed
threshold to satisfy this condition. For a maximum V
IN
of
150V, the lowest programmable threshold is >17V.
LTC2960
12
2960fa
For more information www.linear.com/LTC2960
When a supply voltage is abruptly connected to the input
resonant ringing can occur as a result of series inductance.
The peak voltage could rise to 2x the input supply but in
practice can reach 2.5x if a capacitor with a strong volt
-
age coefficient
is present. If a 12V supply is hot plugged
the resulting ringing could reach the abs max of V
CC
. Any
circuit with an input of more than 7V should be scrutinized
for ringing. Circuit board trace inductances of as little as
10nH can produce significant ringing.
One effective means to eliminate ringing is to include a
10–100Ω resistance in series with the supply input before
the V
CC
capacitor shown in Figure 7(b). This provides damp-
ing for the
resonant circuit but imposes a time constant to
V
CC
. In Figure 7(b), the time constant of RS and C1 iss.
Figure 7. Operation with High Voltage Transients
and Hot Swapping
C1
0.1µF
50V
RZ
143k
PWC1206LF143kJ*
V
CC
Z1
BZX84C30
BV = 30V
V
IN
MAX 200V
LTC2960
(a)
(b)
C1
0.1µF
50V
RS
20
V
IN
V
CC
LTC2960
2960 F07
*TT-IRC
applicaTions inForMaTion

LTC2960HDC-3#TRMPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Supervisory Circuits 36V Nano-Current Two Input Voltage Monitor (ADJ/IN+, 200ms, Active Pull-up, Logic Supply)
Lifecycle:
New from this manufacturer.
Delivery:
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